Low power realization of FIR filters using multirate architectures

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 370-375

  Mehendale, Mahesh ^a   Sherlekar, S D ^a   Venkatesh, G ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUIT LAYOUT; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; STATE SPACE METHODS;

MULTIRATE ARCHITECTURES; WINOGRADS ALGORITHM;

DIGITAL FILTERS;

EID: 0029712838     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)