Analysis of the layout impact on electric fields in interconnect structures using finite element method

Microelectronics Reliability

Volumn 44, Issue 9-11 SPEC. ISS., 2004, Pages 1867-1871

  Hong, Changsoo ^a   Milor, Linda ^a   Lin, M Z ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTRIC FIELDS; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; PERMITTIVITY; PHOTOLITHOGRAPHY;

BREAKDOWN ANALYSIS; ETCH STOP LAYER (ESL); INTERCONNECT STRUCTURES; INTERMETAL DIELECTRICS (IMD);

INTERCONNECTION NETWORKS;

EID: 4544246435     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.07.099     Document Type: Conference Paper

References (7)

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7. J. Noguchi, et at., "TDDB Improvement in Cu Metallization under Bias Stress," Proc. IRPS, 2000, pp. 339-343.