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IEEE International Integrated Reliability Workshop Final Report

Volumn 2002-January, Issue , 2002, Pages 120-124

1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays

(3) Brisbin, Douglas a Strachan, Andy a Chaparala, Prasad a

a NATIONAL SEMICONDUCTOR CORPORATION (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MOS DEVICES; SEMICONDUCTOR JUNCTIONS; TRANSISTORS;

DMOS DEVICES; HIGH DRIVE CURRENT; HOT-CARRIERS; LATERAL DMOS; LAYOUT OPTIMIZATION; ON-RESISTANCE; PERFORMANCE; POWER; POWER MANAGEMENT DEVICE; TRANSISTOR ARRAYS;

HOT CARRIERS;

EID: 44949188233 PISSN: 19308841 EISSN: 23748036 Source Type: Conference Proceeding
DOI: 10.1109/IRWS.2002.1194247 Document Type: Conference Paper

Times cited : (3)

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