Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2002, Pages 105-110

  Brisbin, Douglas ^a   Strachan, Andy ^a   Chaparala, Prasad ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC POTENTIAL; FAILURE ANALYSIS; HOT CARRIERS; INTERFACES (MATERIALS); RELIABILITY; TRANSISTORS;

TRANSISTOR ARRAYS;

MOSFET DEVICES;

EID: 0036084681     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. LDMOS implementation in a 0.35 um BCD technology (BCD6)
2. Complementary 25V LDMOS for analog applications based on 0.6 um BiCMOS technology
3. Experimental study of hot-carrier effects in LDMOS transistors
4. Hot carrier reliability of lateral DMOS transistors
5. Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations
6. Snapback and safe operating area of LDMOS transistors
7. Consistent model for hot-carrier degradation in n-channel and p-channel MOSFET's
8. Hot-electron-induced MOSFET degradation-model, monitor, and improvement