Hot-carrier reliability and design of N-LDMOS transistor arrays

International Integrated Reliability Workshop Final Report

Volumn , Issue , 2001, Pages 44-48

  Brisbin, Douglas ^a   Strachan, Andy ^a   Chaparala, Prasad ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Hot carrier reliability; Lateral DMOS; LDMOS; LDMOS arrays

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; ELECTRIC POTENTIAL; HOT CARRIERS; MOS DEVICES; PORTABLE EQUIPMENT; RELIABILITY;

TRANSISTOR ARRAYS;

CMOS INTEGRATED CIRCUITS;

EID: 0035565642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. LDMOS implementation in a 0.35 um BCD technology (BCD6)
2. Complementary 25V LDMOS for analog applications based on 0.6 um BiCMOS technology
3. Experimental study of hot-carrier effects in LDMOS transistors
4. Hot carrier reliability of lateral DMOS transistors
5. Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations
6. Snapback and safe operating area of LDMOS transistors
7. Hot-electron-induced MOSFET degradation-model, monitor, and improvement