-
1
-
-
0028548950
-
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in mosfets
-
T. Mizuno, J. Okamura, A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs", IEEE Trans. Electron Devices vol. 41, pp. 2216-2221,1994
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 2216-2221
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
2
-
-
6344285724
-
3D statistical simulation of intrinsic fluctuations in decanano mosfets induced by discrete dopants, oxide thickness fluctuations and ler
-
A. Asenov, "3D statistical simulation of intrinsic fluctuations in decanano MOSFETs induced by discrete dopants, oxide thickness fluctuations and LER ", Proc. SISPAD2001, pp. 162-169, 2001
-
(2001)
Proc. SISPAD2001
, pp. 162-169
-
-
Asenov, A.1
-
3
-
-
0033169519
-
Suppression of random dopant-induced threshold voltage fluctuations in sub-0. L-μm mosfet's with epitaxial and delta -doped channels
-
A. Asenov and S. Saini, "Suppression of random dopant-induced threshold voltage fluctuations in sub-0. l-μm MOSFET's with epitaxial and delta -doped channels," IEEE Transactions on Electron Devices, vol. 46, pp. 1718-24, 1999.
-
(1999)
IEEE Transactions on Electron Devices
, vol.46
, pp. 1718-1724
-
-
Asenov, A.1
Saini, S.2
-
4
-
-
33847640837
-
Influence of doping profile and halo implantation on the threshold voltage mismatch of a 0. 13 u. M cmos technology
-
J. A. Croon, E. Augendre, et al., "Influence of Doping Profile and Halo Implantation on the Threshold Voltage Mismatch of a 0. 13 u. m CMOS Technology", Proc. ESSDERC, pp. 579-582, 2002
-
(2002)
Proc. ESSDERC
, pp. 579-582
-
-
Croon, J.A.1
Augendre, E.2
-
5
-
-
84907709834
-
Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron cmos technologies
-
H. P. Tuinhout, "Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies", Proc. ESSDERC, pp. 95-101,2002
-
(2002)
Proc. ESSDERC
, pp. 95-101
-
-
Tuinhout, H.P.1
-
6
-
-
17944400303
-
CMOS device optimization for mixed-signal technologies
-
P. A. Stolk, H. P. Tuinhout, et al., "CMOS Device Optimization for Mixed-Signal Technologies", Tech. Digest 1EDM, pp. 215-218, 2001
-
(2001)
Tech. Digest 1EDM
, pp. 215-218
-
-
Stolk, P.A.1
Tuinhout, H.P.2
-
7
-
-
84948782220
-
Integrated atomistic process and device simulation of decananometre mosfets
-
A. Asenov, M. Jaraiz, S. Roy, G. Roy, et al., "Integrated Atomistic. Process and Device Simulation of Decananometre MOSFETs", Proc. SISPAD2002, pp. 87-90, 2002
-
(2002)
Proc. SISPAD2002
, pp. 87-90
-
-
Asenov, A.1
Jaraiz, M.2
Roy, S.3
Roy, G.4
-
8
-
-
0035716657
-
High performance 35 nm gate length cmos with no oxynitride gate dielectric and ni salic1de
-
S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, et al., "High Performance 35 nm Gate Length CMOS with NO Oxynitride Gate Dielectric and Ni SALIC1DE", Tech. Digest IEDM, 2001
-
(2001)
Tech. Digest IEDM
-
-
Inaba, S.1
Okano, K.2
Matsuda, S.3
Fujiwara, M.4
|