Synergistic Fault-Tolerance for Memory Chips

IEEE Transactions on Computers

Volumn 41, Issue 9, 1992, Pages 1078-1087

  Stapper, Charles H ^a   Lee, Hsing San ^a  

^a IBM   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; MICROPROCESSOR CHIPS; PROBABILITY; RANDOM ACCESS STORAGE; REDUNDANCY; VLSI CIRCUITS;

BIRTHDAY PROBLEM; BITLINE REDUNDANCY; ERROR CORRECTING CODES; SYNERGISTIC FAULT TOLERANCE; VLSI FABRICATION YIELD ENHANCEMENT; VLSI MEMORY CHIP; WORDLINE REDUNDANCY;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0026926892     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.165390     Document Type: Article

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