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Volumn , Issue , 2007, Pages 400-403

Statistical modeling for the minimum standby supply voltage of a full SRAM array

Author keywords

[No Author keywords available]

Indexed keywords

DATA RETENTION VOLTAGE (DRV); EUROPEAN; GENERALIZED PARETO DISTRIBUTION (GPD); HIGH ACCURACY; INDIVIDUAL (PSS 544-7); LEAKAGE POWER REDUCTION; LOWER BOUNDS; MEMORY ARRAYS; MONTE CARLO SIMULATION (MCS); NEW MODEL; SOLID-STATE CIRCUITS CONFERENCE; STATIC NOISE MARGIN (SNM); STATISTICAL DISTRIBUTIONS; STATISTICAL MODELLING; SUPPLY VOLTAGES; SUPPLY-VOLTAGE SCALING; WITHIN DIE (WID);

EID: 44849133673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430327     Document Type: Conference Paper
Times cited : (45)

References (8)
  • 1
    • 0036049564 scopus 로고    scopus 로고
    • High-performance and low-power challenges for sub-70 nm microprocessor circuits
    • R. Krishnamurthy, et al., "High-performance and low-power challenges for sub-70 nm microprocessor circuits," CICC, 2002.
    • (2002) CICC
    • Krishnamurthy, R.1
  • 2
    • 2942687683 scopus 로고    scopus 로고
    • SRAM leakage suppression by minimizing standby supply voltage
    • H. Qin, et. al., "SRAM leakage suppression by minimizing standby supply voltage," ISQED, 2004.
    • (2004) ISQED
    • Qin, H.1    et., al.2
  • 3
    • 34548303547 scopus 로고    scopus 로고
    • Statistical Blockade: A novel method for very fast Monte Carlo simulation of rare circuit events, and its application
    • A. Singhee and R. A. Rutenbar, "Statistical Blockade: A novel method for very fast Monte Carlo simulation of rare circuit events, and its application," DATE, 2007.
    • (2007) DATE
    • Singhee, A.1    Rutenbar, R.A.2
  • 4
    • 0023437909 scopus 로고
    • Static noise margin analysis of MOS SRAM cells
    • Oct
    • E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells," JSSC, vol. SC-22, no. 5, pp. 748-754, Oct. 1978.
    • (1978) JSSC , vol.SC-22 , Issue.5 , pp. 748-754
    • Seevinck, E.1    List, F.2    Lohstroh, J.3
  • 5
    • 33746369469 scopus 로고    scopus 로고
    • Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    • July
    • B. Calhoun and A. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS", JSSC, vol. 41, No. 7, pp. 1673-1679, July 2006.
    • (2006) JSSC , vol.41 , Issue.7 , pp. 1673-1679
    • Calhoun, B.1    Chandrakasan, A.2
  • 6
    • 34748817701 scopus 로고    scopus 로고
    • Analyzing and modeling process balance for sub-threshold circuit design
    • J. Ryan, J. Wang, and B. Calhoun, "Analyzing and modeling process balance for sub-threshold circuit design," GLSVLSI, 2007.
    • (2007) GLSVLSI
    • Ryan, J.1    Wang, J.2    Calhoun, B.3
  • 7
    • 0036858210 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    • Nov
    • J. W. Tschanz, J. T. Kao, et. al, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage", JSSC, vol. 37, No. 11, pp. 1396-1402, Nov 2002.
    • (2002) JSSC , vol.37 , Issue.11 , pp. 1396-1402
    • Tschanz, J.W.1    Kao, J.T.2    et., al.3
  • 8
    • 0042912833 scopus 로고    scopus 로고
    • Simulation of intrinsic parameter fluctuations in decananometer and nanometer-Scale MOSFETs
    • A. Asenov, et.al, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-Scale MOSFETs," IEEE Trans. Electron Devices 50, pp.1837-1852, 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , pp. 1837-1852
    • Asenov, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.