Interleaving partial bus-invert coding for low power reconfiguration of FPGAs

ICVC 1999 - 6th International Conference on VLSI and CAD

Volumn , Issue , 1999, Pages 549-552

  Yoo, Sungjoo ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84941356767     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVC.1999.820997     Document Type: Conference Paper

References (4)

1. Xilinx Inc., 'Xilinx part information.', http://www.xilinx.com/partinfo/.
2. SHIN, Y. CHAE, S. and CHOI. K.: 'Reduction of bus transitions with partial bus-invert coding'. Electron. Lett., 1998,34, (7), pp. 642-643
3. STAN, M.R. and BURLESON, W.R: 'Bus-invert coding for low-power I/O', IEEE Transactions on VLSI Systems, 1995, 3, (I), pp. 49-58
4. BENINI, L., DE MICHELI, G., MACII, E., PONCINO, M., and QUER, S.: 'System-level power optimization of special purpose applications: The Beach Solution', Proceedings of International Symposium on Low Power Electronics and Design, 1997, pp.24-29