On reducing transitions through data modifications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 82-88

  Murgai, Rajeev ^a   Fujita, Masahiro ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA MODIFICATION; ERROR TOLERANCE; FOLLOWING PROBLEM; GREEDY STRATEGIES; LINEAR-TIME; OPTIMUM SOLUTION; TOTAL POWER; UNIFORM DISTRIBUTION;

EXHIBITIONS; SECURITY OF DATA;

DATA REDUCTION;

EID: 46149117922     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761101     Document Type: Conference Paper

References (13)

1. J. Bunda, W. C. Athas, and D. Fussell. Evaluating Power Implications of CMOS Microprocessor Design Decisions. In International Workshop on Low Power Design, pages 147-152, April 1994.
2. A. Chandrakasan,T. Sheng, and R. W. Brodersen. LowPower CMOS Digital Design. In Journal of Solid State Circuits, pages 473-484, April 1992.
3. K. Y. Chao and D. F. Wong. Low Power Considerations in Floorplan Design. In International Workshop on Low Power Design, pages 45-50, April 1994.
4. J. Cong, C. K. Koh, and K. S. Leung. Wiresizing with Driver Sizing for Performance and Power Optimization. In Interna-tional Workshop on Low Power Design, pages 81-86, April 1994.
5. Experienced Motorola Designer. Personal comm., April 1995.
6. P. Duncan, S. Swamy, and R. Jain. Low-Power DSP Cir-cuit Design Using Retimed Maximally Parallel Architectures. In Proceedings of the 1st Symposium on Integrated Systems, pages 266-275, March 1993.
7. V. Hirendu and M. Pedram. PCUBE: A Performance Driven Placement Algorithm for Lower Power Designs. In Proceed-ings of Euro-DAC, pages 72-77, 1993.
8. R. Murgai, M. Fujita, and S. C. Krishnan. Data Sequencing for Minimum-transition Transmission. In VLSI'97, August 1997.
9. R. Murgai, M. Fujita, and A. Oliveira. Using Complementa-tion and Resequencing To Minimize Transitions. In Proceed-ings of the Design Automation Conference, pages 694-697, June 1998.
10. K. Roy and S. Prasad. SYCLOP: Synthesis of CMOS Logic for Low Power Applications. In Proceedings of the Int'l Con-ference on Computer Design: VLSI in Computers and Pro-cesors, pages 464-467, October 1992.
11. A. Shen, S. Devadas, J. White, A. Ghosh, and K. Keutzer. A Combinational Logic Design Methodology Targeting Low Power Applications. In MIT Technical Report (available from the authors), February 1993.
12. C. H. Tan and J. Allen. Minimization of Power in VLSI Cir-cuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation. In International Workshop on Low Power Design, pages 75-80, April 1994.
13. V. Tiwari, P. Ashar, and S. Malik. Technology Mapping for Low Power. In Proceedings of the 30th Design Automation Conference, pages 74-79, June 1993.