High-frequency performance of subthreshold SOI MESFETs

IEEE Electron Device Letters

Volumn 25, Issue 9, 2004, Pages 652-654

  Yang, Jinman ^a   Spann, John ^a   Anderson, Robert ^a   Thornton, Trevor ^a  

^a AZ 85281   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; MIXER CIRCUITS; SCHOTTKY BARRIER DIODES; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

DRAIN CURRENTS; DRAIN VOLTAGES; MIXED SIGNAL MICROPOWER CIRCUIT DESIGN; SUBTHRESHOLD OPERATION;

MESFET DEVICES;

EID: 4444331201     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.834245     Document Type: Article

References (13)

1. τ RFMOS and versatile, high-Q passive components for cost/performance optimization," in IEDM Tech. Dig., 2003, pp. 2.5.1-2.5.4.
2. D. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley, and R. Chan, "High-frequency response of 100 nm integrated CMOS transistors with high-κ gate dielectrics," in IEDM Tech. Dig., 2001, pp. 10.16.11-10.16.14.
3. M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose, and H. Iwai, "0.15-micrometer RF CMOS technology compatible with logic CMOS for low-voltage operation," IEEE Trans. Electron Devices, vol. 45, pp. 737-742, Apr. 1998.
4. S. Narasimha, A. Ajmera, H. Park, D. Schepis, N. Zamdmer, K. A. Jenkins, J.-O. Plouchart, W.-H. Lee, J. Mezzapelle, J. Bruley, B. Doris, J. W. Sleight, S. K. Fung, S. H. Ku, A. C. Mocuta, I. Yang, P. V. Gilbert, K. P. Muller, P. Agnello, and J. Welser, "High-performance sub-40-nm CMOS devices on SOI for the 70-nm technology node," in IEDM Tech. Dig., 2001, pp. 29.22.21-29.22.24.
5. max with dual offset-implanted source-drain extension structure for RF/analog and logic applications," in IEDM Tech. Dig., 2001, pp. 10.13.11-10.13.14.
6. C. L. Chen, R. H. Mathews, J. A. Burns, P. W. Wyatt, D. R. Yost, C. K. Chen, M. Fritze, J. M. Knecht, V. Suntharalingam, A. Soares, and C. L. Keast, "High-frequency characterization of sub-0.25-mu m fully depleted silicon-on-insulator MOSFETs," IEEE Electron Device Lett., vol. 21, pp. 497-499, Apr. 2000.
7. A. O. Adan, T. Yoshimasu, S. Shitara, N. Tanba, and M. Fukumi, "Linearity and low-noise performance of SOI MOSFETs for RF applications," IEEE Trans. Electron Devices, vol. 49, pp. 881-888, May 2002.
8. E. Vittoz, "Micropower techniques," in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, J. Franca and Y. Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994.
9. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999.
10. J. R. Brews, "Carrier-density fluctuations and igfet mobility near threshold," J. Appl. Phys., vol. 46, pp. 2193-2203, 1975.
11. J. T. C. Chen and R. S. Muller, "Carrier mobilities at weakly inverted silicon surfaces," J. Appl. Phys., vol. 45, pp. 828-834, 1974.
12. J. Spann, Z. Wu, P. Jaconelli, J. Yang, and T. J. Thornton, "Schottky junction transistors for micropower RFICs," in Proc. IEEE Radio Frequency Integrated Circuit Symp., Seattle, WA, 2002.
13. T. J. Thornton, "Physics and applications of the Schottky junction transistor," IEEE Trans. Electron Devices, vol. 48, pp. 2421-2427, Dec. 2001.