Novel video memory reduces 45% of bitline power using majority logic and data-bit reordering

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 6, 2008, Pages 620-627

  Fujiwara, Hidehiro ^a,b   Nii, Koji ^a,b   Noguchi, Hiroki ^b   Miyakoshi, Junichi ^b   Murachi, Yuichiro ^b   Morita, Yasuhiro ^a,b   Kawaguchi, Hiroshi ^a,b   Yoshimoto, Masahiko ^a,b  

^a IEEE

^b KOBE UNIVERSITY   (Japan)

Author keywords

Data bit reordering; Low power SRAM; Majority logic; Real time image processing; Two port SRAM

Indexed keywords

DATA RECORDING; LOGIC CIRCUITS; REAL TIME SYSTEMS; STATISTICAL METHODS;

REAL TIME VIDEO PROCESSING;

STATIC RANDOM ACCESS STORAGE;

EID: 44249093269     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000249     Document Type: Conference Paper

References (11)

1. ITRS, "International Technology Roadmap for Semiconductors," 2005. [Online]. Available: http://www.itrs.net/Common/2005ITRS/ Home2005.htm
2. J. Miyakoshi, Y. Murachi, K. Hamano, T. Matsuno, M. Miyama, and M. Yoshimoto, "A low-power systolic array architecture for block-matching motion estimation," IEICE Trans. Electron., vol. E88-C, no. 4, pp. 559-569, Apr. 2005.
3. Y. Murachi, K. Hamano, T. Matsuno, J. Miyakoshi, M. Miyama, and M. Yoshimoto, "A 95 mW MPEG2 MP@HL motion estimation processor core for portable high-resolution video application," IEICE Trans. Fundamentals, vol. E88-A, no. 12, pp. 3492-3499, Dec. 2005.
4. S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, S. Michinaka, K. Yahagi, A. Oue, T. Kodama, N. Matsumoto, T. Kamei, M. Saito, T. Miyamori, G. Ootomo, and M. Matsui, "A single-chip MPEG-2 codec based on customizable media embedded processor," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 530-540, Mar. 2003.
5. Y.-W. Huang, T.-C. Chen, C.-H. Tsai, C.-Y. Chen, T.-W. Chen, C.-S. Chen, C.-F. Shen, S.-Y. Ma, T.-C. Wang, B.-Y. Hsieh, H.-C. Fang, and L.-G. Chen, "A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications," in Proc. IEEE Int. Solid-State Circuits Conf., Jan. 2005, pp. 128-129.
6. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A read-static-noise-margin-free SRAM cell for low-Kid and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-12.1, Jan. 2006.
7. J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, F. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, and D. Wendel, "Implementation of the CELL broadband engine in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2007, pp. 322-323.
8. H. Yamauchi, T. Suzuki, and Y. Yamagami, "A 1R/1W SRAM cell design to keep cell current and area saving against simultaneous read/ write disturbed accesses," IEICE Trans. Electron., vol. E90-C, no. 4, pp. 749-757, Apr. 2007.
9. M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM," IEEE J. Solid-State Circuits, vol. SSC-18, no. 5, pp. 479-485, Oct. 1983.
10. M. R. Stan and W. P. Burleson, "Bus-Invert coding for low power I/O," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp. 49-58, Mar. 1995.
11. Y. Shin and K. Choi, "Narrow bus encoding for low power systems," in Proc. Asia South Pacific Des. Autom. Conf., Jan. 2000, pp. 217-220.