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Volumn , Issue , 2000, Pages 217-220

Narrow bus encoding for low power systems

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATTERNS; DECODER CIRCUITS; DSP APPLICATION; LOW-POWER SYSTEMS; PERFORMANCE DEGRADATION; POWER SAVINGS; RANDOM PATTERN; TRANSITION SIGNALING;

EID: 0003762912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368609     Document Type: Conference Paper
Times cited : (18)

References (13)
  • 2
    • 0028448788 scopus 로고
    • Power consumption estimation in CMOS VLSI chips
    • June
    • D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 663-670, June 1994.
    • (1994) IEEE Journal of Solid-State Circuits , vol.29 , Issue.6 , pp. 663-670
    • Liu, D.1    Svensson, C.2
  • 3
    • 0003147684 scopus 로고    scopus 로고
    • Low power architecture design and compilation technique for high-performance processors
    • C. L. Su, C. Y. Tsui, and A. M. Despain, "Low power architecture design and compilation technique for high-performance processors," in Proc. IEEE COMPCON, Feb. 1994, pp. 209-214.
    • Proc. IEEE COMPCON, Feb. 1994 , pp. 209-214
    • Su, C.L.1    Tsui, C.Y.2    Despain, A.M.3
  • 5
    • 35048834531 scopus 로고
    • Bus-invert coding for low-power I/O
    • Mar.
    • M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. on VLSI Systems, vol. 3, no. 1, pp. 49-58, Mar. 1995.
    • (1995) IEEE Trans. on VLSI Systems , vol.3 , Issue.1 , pp. 49-58
    • Stan, M.R.1    Burleson, W.P.2
  • 6
    • 0031342532 scopus 로고    scopus 로고
    • Low-power encodings for global communication in CMOS VLSI
    • Dec.
    • M. R. Stan and W. P. Burleson, "Low-power encodings for global communication in CMOS VLSI," IEEE Trans. on VLSI Systems, vol. 5, no. 4, pp. 444-455, Dec. 1997.
    • (1997) IEEE Trans. on VLSI Systems , vol.5 , Issue.4 , pp. 444-455
    • Stan, M.R.1    Burleson, W.P.2
  • 10
    • 0003713065 scopus 로고
    • Integrated circuit having outputs configured for reduced state changes
    • May U.S. Patent 4667337
    • R. J. Fletcher, "Integrated circuit having outputs configured for reduced state changes," May 1987, U.S. Patent 4667337.
    • (1987)
    • Fletcher, R.J.1
  • 11
    • 0000440896 scopus 로고
    • Architectural power analysis: The dual bit type method
    • June
    • P. Landman and J. Rabaey, "Architectural power analysis: the dual bit type method," IEEE Trans. on VLSI Systems, vol. 3, no. 2, pp. 173-187, June 1995.
    • (1995) IEEE Trans. on VLSI Systems , vol.3 , Issue.2 , pp. 173-187
    • Landman, P.1    Rabaey, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.