A low-power systolic array architecture for block-matching motion estimation

IEICE Transactions on Electronics

Volumn E88-C, Issue 4, 2005, Pages 559-569

  Miyakoshi, Junichi ^a   Murachi, Yuichiro ^a   Hamano, Koji ^a   Matsuno, Tetsuro ^a   Miyama, Masayuki ^a   Yoshimoto, Masahiko ^a,b  

^a KANAZAWA UNIVERSITY   (Japan)

^b KOBE UNIVERSITY   (Japan)

Author keywords

Block matching; H.264; Motion estimation; MPEG

Indexed keywords

COMPUTATION THEORY; COMPUTER ARCHITECTURE; IMAGE CODING; IMAGE COMPRESSION; OPTICAL RESOLVING POWER; VLSI CIRCUITS;

BLOCK-MATCHING; H.264; MPEG; PROCESSING ELEMENT (PE) ARRAY;

MOTION ESTIMATION;

EID: 29144487232     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e88-c.4.559     Document Type: Article

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