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Volumn 85, Issue 5-6, 2008, Pages 1375-1378

Fabrication of 22 nm T-gates for HEMT applications

Author keywords

Electron beam lithography; HEMT; Reactive ion etching; T gate

Indexed keywords

ANISOTROPIC ETCHING; ELECTRON BEAM LITHOGRAPHY; ELECTRON MOBILITY; SILICON NITRIDE; TRANSISTORS;

EID: 44149110404     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2008.01.058     Document Type: Article
Times cited : (11)

References (7)
  • 2
    • 0032680212 scopus 로고    scopus 로고
    • 30-nm-gate InP-based lattice-matched high electron mobility transistors with 350 GHz cutoff frequency
    • Suemitsu T., Tetsuyoshi I., Yokoyama H., Enoki T., Ishii Y., and Tamamura T. 30-nm-gate InP-based lattice-matched high electron mobility transistors with 350 GHz cutoff frequency. Jpn. J. Appl. Phys. 38 (1999) L154-L156
    • (1999) Jpn. J. Appl. Phys. , vol.38
    • Suemitsu, T.1    Tetsuyoshi, I.2    Yokoyama, H.3    Enoki, T.4    Ishii, Y.5    Tamamura, T.6
  • 3
    • 33847120746 scopus 로고    scopus 로고
    • S. Kwang-Seok, K. Dae-Hyun, Nanometer scale InGaAs HEMT technology for ultra high speed IC, in: Indium Phosphide and Related Materials, Princeton, NJ, 2006, pp. 30-35.
    • S. Kwang-Seok, K. Dae-Hyun, Nanometer scale InGaAs HEMT technology for ultra high speed IC, in: Indium Phosphide and Related Materials, Princeton, NJ, 2006, pp. 30-35.
  • 4
    • 0034317718 scopus 로고    scopus 로고
    • Fabrication of 30 nm T gates using SiN as a supporting and definition layer
    • Chen Y., Edgar D., Li X., Macintyre D., and Thoms S. Fabrication of 30 nm T gates using SiN as a supporting and definition layer. J. Vac. Sci. Technol. B 18 6 (2000) 3521
    • (2000) J. Vac. Sci. Technol. B , vol.18 , Issue.6 , pp. 3521
    • Chen, Y.1    Edgar, D.2    Li, X.3    Macintyre, D.4    Thoms, S.5
  • 6
    • 34547873937 scopus 로고    scopus 로고
    • Low-hydrogen-content silicon nitride deposited at room temperature by inductively coupled plasma deposition
    • Zhou H., Elgaid K., Wilkinson C., and Thayne I. Low-hydrogen-content silicon nitride deposited at room temperature by inductively coupled plasma deposition. Jpn. J. Appl. Phys. 45 10B (2006) 8388-8392
    • (2006) Jpn. J. Appl. Phys. , vol.45 , Issue.10 B , pp. 8388-8392
    • Zhou, H.1    Elgaid, K.2    Wilkinson, C.3    Thayne, I.4
  • 7
    • 44149114531 scopus 로고    scopus 로고
    • A low damage SiN sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs
    • Li X., Hill R., Zhou H., Wilkinson C., and Thayne I. A low damage SiN sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs. Microelectron. Eng. 85 (2008) 996-999
    • (2008) Microelectron. Eng. , vol.85 , pp. 996-999
    • Li, X.1    Hill, R.2    Zhou, H.3    Wilkinson, C.4    Thayne, I.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.