Manufacturable processes for ≤ 32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances

IEEE Transactions on Electron Devices

Volumn 55, Issue 5, 2008, Pages 1259-1264

  Noori, Atif M ^a   Balseanu, Mihaela ^a   Boelen, Pieter ^a   Cockburn, Andrew ^a   Demuynck, Steven ^b   Felch, Susan ^a   Gandikota, Srinivas ^a   Gelatos, A Jerry ^a   Khandelwal, Amit ^a   Kittl, Jorge A ^b   Lauwers, Anne ^b   Lee, Wen Chin ^c   Lei, Jianxin ^a   Mandrekar, Tushar ^a   Schreutelkamp, Robert ^a   Shah, Kavita ^a   Thompson, Scott E ^d   Verheyen, Peter ^b   Wang, Ching Ya ^c   Xia, Li Qun ^a   Arghavani, Reza ^a   more..

^a APPLIED MATERIALS INC   (United States)

^b IMEC   (Belgium)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d University of Florida   (United States)

Author keywords

Cu contacts; External resistance; Laser anneal; Silicide; Strain engineering

Indexed keywords

ANNEALING; COMPUTER SIMULATION; COPPER; OPTIMIZATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICIDES; STRAIN; TENSILE STRESS;

CMOS ENHANCEMENT; EXTERNAL PARASITIC RESISTANCES; STRAIN ENGINEERING; STRAIN-ENGINEERED CHANNEL; SYNCHRONOUS OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 43749102080     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.919558     Document Type: Article

References (12)

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