Fault modeling of RF blocks based on noise analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Da̧browski, Jerzy ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; DEMODULATION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GAIN CONTROL; IMPEDANCE MATCHING (ELECTRIC); MATHEMATICAL MODELS; MIXER CIRCUITS; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE; TRANSISTORS;

FAULT MODELING; NOISE ANALYSIS; RF BLOCKS; SPOT DEFECTS;

TRANSCEIVERS;

EID: 4344638247     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A.Grochowski, et al, "Integrated Circuits Testing for Quality Assurance in Manufacturing: History, Current Status, and Future Trends", IEEE Trans.CAS-II; Analog and Digital Signal Proc., pp. 610-633, vol.44, no.8, Aug.1997
2. Y.Xing, "Defect-Oriented Testing of Mixed-Signal ICs: Some Industrial Experience", IEEE Intl. Test Conf., pp.678-687, 1998.
3. D.Lupea et al., "RF-BiST : Loopback Spectral signature Analysis", Proc. of DATE'03, 6 pp., 2003
4. J.Dabrowski, "BiST Model for IC RF-Transceiver Front-End", Proc. of DFT'03, pp.295-302, 2003
5. M.Sachdev, B.Atzema, "Industrial Relevance of Analog IFA: A Fact or a Fiction", IEEE Intl. Test Conf., pp.61-70, 1995
6. M.J.Ohletz, "Realistic Fault Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits", IEEE Intl. Test Conf., pp.776-785, 1996
7. K.Saab, et al., "Closing the Gap Between Analog and Digital Testing", IEEE Trans. CAD of IC&Sys., vol.20, no.2, pp.307-314, Feb.2001