BiST model for IC RF-transceiver front-end

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 295-302

  Dąbrowski, Jerzy ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUITS; NOISE FIGURE; SPACE OPTICS; TRANSCEIVERS;

BASE BANDS; BIST TECHNIQUES; CMOS PROCESSS; FUNCTIONAL LEVELS; GSM TRANSCEIVERS; MASS PRODUCTION; RF TRANSCEIVERS; SPOT DEFECTS;

RADIO TRANSCEIVERS;

EID: 84971282302     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250124     Document Type: Conference Paper

References (11)

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