Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 776-785

  Ohletz, Michael J ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DEFECTS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; OPERATIONAL AMPLIFIERS; SEMICONDUCTOR DEVICE MODELS;

LOCAL LAYOUT REALISTIC FAULT MAPPING;

CMOS INTEGRATED CIRCUITS;

EID: 0030409505     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)