-
3
-
-
0003585771
-
Introduction to microelectronic fabrication
-
G. W. Neudeck and R. F. Pierret, Eds. New York: Addison-Wesley
-
R. C. Jaeger, "Introduction to microelectronic fabrication," in Modular Series on Solid State Devices, G. W. Neudeck and R. F. Pierret, Eds. New York: Addison-Wesley, 1993, vol. 3.
-
(1993)
Modular Series on Solid State Devices
, vol.3
-
-
Jaeger, R.C.1
-
5
-
-
0025433611
-
The use and evaluation of yield models in integrated circuit manufacturing
-
June
-
J. A. Cunningham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semiconduct. Manufact., vol. 3, pp. 60-71, June 1990.
-
(1990)
IEEE Trans. Semiconduct. Manufact.
, vol.3
, pp. 60-71
-
-
Cunningham, J.A.1
-
6
-
-
0031344282
-
Gate CD control for a 0.35 um logic technology
-
San Francisco, CA, Oct
-
T. Boynton, W. Yu, and J. Pak, "Gate CD control for a 0.35 um logic technology," in Proc. IEEE Int. Symp. Semiconductor Manufacturing Conf., San Francisco, CA, Oct. 1997, pp. F9-F12.
-
(1997)
Proc. IEEE Int. Symp. Semiconductor Manufacturing Conf.
-
-
Boynton, T.1
Yu, W.2
Pak, J.3
-
7
-
-
0034474970
-
Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits
-
San Jose, CA, Nov
-
M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits," in Proc. Technical Dig, 2000 IEEE/ACM Int. Conf. Computer Aided Design, San Jose, CA, Nov. 2000, pp. 62-67.
-
(2000)
Proc. Technical Dig, 2000 IEEE/ACM Int. Conf. Computer Aided Design
, pp. 62-67
-
-
Orshansky, M.1
Milor, L.2
Chen, P.3
Keutzer, K.4
Hu, C.5
-
8
-
-
0034839492
-
Measurement and analysis of reticle and wafer level contributions to total CD variation
-
Edinburgh, U.K., May
-
M. E. Preil and C. A. Mack, "Measurement and analysis of reticle and wafer level contributions to total CD variation," in Proc. SPIE Int. Society Optical Eng., vol. 4404, Edinburgh, U.K., May 2001, pp. 144-152.
-
(2001)
Proc. SPIE Int. Society Optical Eng.
, vol.4404
, pp. 144-152
-
-
Preil, M.E.1
Mack, C.A.2
-
9
-
-
85013007355
-
Critical dimension sampling planning for sub-0.25 micron processes
-
Boston, MA, Sept
-
R. C. Elliot, R. K. Nurani, D. Gudmundsson, M. Preil, R. Nasongkhla, and J. G. Shanthikumar, "Critical dimension sampling planning for sub-0.25 micron processes," in Proc. 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conf. Workshop, Boston, MA, Sept. 1999, pp. 139-142.
-
(1999)
Proc. 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conf. Workshop
, pp. 139-142
-
-
Elliot, R.C.1
Nurani, R.K.2
Gudmundsson, D.3
Preil, M.4
Nasongkhla, R.5
Shanthikumar, J.G.6
-
10
-
-
4344697760
-
A novel methodology of critical dimension statistical process control
-
Hsinchu, Taiwan, June
-
C. P. Chen, A. Shyu, P. Liou, R. Q. Leu, K. Huang, J. Y. Lin, T. H. Yang, H. C. Liu, M. I. Ting, and Y. C. Shih, "A novel methodology of critical dimension statistical process control," in Proc. 1998 Semiconductor Manufacturing Technology Workshop, Hsinchu, Taiwan, June 1998, pp. 124-130.
-
(1998)
Proc. 1998 Semiconductor Manufacturing Technology Workshop
, pp. 124-130
-
-
Chen, C.P.1
Shyu, A.2
Liou, P.3
Leu, R.Q.4
Huang, K.5
Lin, J.Y.6
Yang, T.H.7
Liu, H.C.8
Ting, M.I.9
Shih, Y.C.10
-
11
-
-
0030414598
-
Inter-and intra-die polysilicon critical dimension variation
-
Austin, TX, Oct
-
B. E. Stine, D. S. Boning, J. E. Chung, D. A. Bell, and E. Equi, "Inter-and intra-die polysilicon critical dimension variation," in Proc. SPIE Int. Society Optical Eng., vol. 2874, Austin, TX, Oct. 1996, pp. 27-35.
-
(1996)
Proc. SPIE Int. Society Optical Eng.
, vol.2874
, pp. 27-35
-
-
Stine, B.E.1
Boning, D.S.2
Chung, J.E.3
Bell, D.A.4
Equi, E.5
-
12
-
-
0031077147
-
Analysis and decomposition of spatial variation in integrated circuit processes and devices
-
B. E. Stine, D. S. Boning, and J. E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE Trans. Semiconduct. Manufact., vol. 10, no. 1, pp. 24-41, 1997.
-
(1997)
IEEE Trans. Semiconduct. Manufact.
, vol.10
, Issue.1
, pp. 24-41
-
-
Stine, B.E.1
Boning, D.S.2
Chung, J.E.3
-
13
-
-
0032272376
-
Within-chip variability analysis
-
San Francisco, CA, Dec
-
S. R. Nassif, "Within-chip variability analysis," in Tech. Dig. 1998 IEEE Int. Electron Devices Meeting, San Francisco, CA, Dec. 1998, pp. 283-286.
-
(1998)
Tech. Dig. 1998 IEEE Int. Electron Devices Meeting
, pp. 283-286
-
-
Nassif, S.R.1
-
14
-
-
0026817966
-
Experimental verification of a fundamental model for multiwafer low-pressure chemical vapor deposition of polysilicon
-
T. A. Badgwell, T. F. Edgar, I. Trachtenberg, and J. K. Elliott, "Experimental verification of a fundamental model for multiwafer low-pressure chemical vapor deposition of polysilicon," J. Electrochemical Soc., vol. 139, no. 2, pp. 524-532, 1992.
-
(1992)
J. Electrochemical Soc.
, vol.139
, Issue.2
, pp. 524-532
-
-
Badgwell, T.A.1
Edgar, T.F.2
Trachtenberg, I.3
Elliott, J.K.4
-
15
-
-
0017675543
-
Statistical methods for estimating variance components for integrated circuits device parameters
-
T. F. Retajczyk Jr. and W. Larsen, "Statistical methods for estimating variance components for integrated circuits device parameters," Microelectron. Reliability, vol. 16, no. 5, pp. 561-566, 1977.
-
(1977)
Microelectron. Reliability
, vol.16
, Issue.5
, pp. 561-566
-
-
Retajczyk Jr., T.F.1
Larsen, W.2
-
16
-
-
0028386362
-
Enhancing the analysis of variance (ANOVA) technique with graphical analysis and its application to wafer processing equipment
-
Mar.
-
L. K. Garling and G. P. Woods, "Enhancing the analysis of variance (ANOVA) technique with graphical analysis and its application to wafer processing equipment," IEEE Trans. Components, Hybrids, Manufact. Technol. - Part A, vol. 17, pp. 149-152, Mar. 1994.
-
(1994)
IEEE Trans. Components, Hybrids, Manufact. Technol. - Part A
, vol.17
, pp. 149-152
-
-
Garling, L.K.1
Woods, G.P.2
-
17
-
-
0028533156
-
Monitoring variance components
-
E. Yashchin, "Monitoring variance components," Technometrics, vol. 36, no. 4, pp. 379-393, 1994.
-
(1994)
Technometrics
, vol.36
, Issue.4
, pp. 379-393
-
-
Yashchin, E.1
-
18
-
-
84953122460
-
Shewhart-type charts in nonstandard situations
-
K. C. B. Roes and R. J. M. M. Does, "Shewhart-type charts in nonstandard situations," Technometrics, vol. 37, no. 1, pp. 15-40, 1995.
-
(1995)
Technometrics
, vol.37
, Issue.1
, pp. 15-40
-
-
Roes, K.C.B.1
Does, R.J.M.M.2
-
19
-
-
0034664151
-
Improving the manufacturing process quality and capability using experimental design: A case study
-
J. Antony, "Improving the manufacturing process quality and capability using experimental design: A case study," Int. J. Production Res., vol. 38, no. 12, pp. 2607-2618, 2000.
-
(2000)
Int. J. Production Res.
, vol.38
, Issue.12
, pp. 2607-2618
-
-
Antony, J.1
-
20
-
-
0034691906
-
A systems approach to photolithography process optimization in an electronics manufacturing environment
-
A. Doniavi, A. R. Mileham, and L. B. Newnes, "A systems approach to photolithography process optimization in an electronics manufacturing environment," Int. J. Production Res., vol. 38, no, 11, pp. 2515-2528, 2000.
-
(2000)
Int. J. Production Res.
, vol.38
, Issue.11
, pp. 2515-2528
-
-
Doniavi, A.1
Mileham, A.R.2
Newnes, L.B.3
-
21
-
-
0010769451
-
Experimental design issues in simulation with examples from semiconductor manufacturing
-
Arlington, VA, Dec
-
S. Hood and P. D. Welch, "Experimental design issues in simulation with examples from semiconductor manufacturing," in Proc. 1992 Winter Simulation Conf., Arlington, VA, Dec. 1992, pp. 255-263.
-
(1992)
Proc. 1992 Winter Simulation Conf.
, pp. 255-263
-
-
Hood, S.1
Welch, P.D.2
-
22
-
-
0023348325
-
Orthogonal design for process optimization and its application in plasma etching
-
May
-
G. Z. Yin and D. W. Jillie, "Orthogonal design for process optimization and its application in plasma etching," Solid State Technol., pp. 127-132, May 1987.
-
(1987)
Solid State Technol.
, pp. 127-132
-
-
Yin, G.Z.1
Jillie, D.W.2
|