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Volumn 18, Issue 8, 2008, Pages 1173-1177

Fabrication of a memory chip by a complete self-assembly process using state-of-the-art multilevel cell (MLC) technology

Author keywords

[No Author keywords available]

Indexed keywords

ADSORPTION; CHIP SCALE PACKAGES; ELECTRON BEAMS; EVAPORATION; MOLECULAR ELECTRONICS; SELF ASSEMBLY;

EID: 43249116142     PISSN: 1616301X     EISSN: 16163028     Source Type: Journal    
DOI: 10.1002/adfm.200700937     Document Type: Article
Times cited : (7)

References (26)
  • 3
  • 6
    • 0034644227 scopus 로고    scopus 로고
    • P. Ball, Nature 2000, 406, 118.
    • (2000) Nature , vol.406 , pp. 118
    • Ball, P.1
  • 8
    • 43249089837 scopus 로고    scopus 로고
    • The news of this invention was released to the press in April 2007 found in the link, given by 20, 21 +22, 23, 2n-1, if there are n numbers of switches, the sum is the largest number that one can store. Now, the sum of this series is given by S =a(rn-1, r-1, where a is the first term of the series, r is the multiplication factor. Therefore for a binary system the sum is S(2, 1(2n-1)/2-1 and for tetranary system it is S(4, 1(4n-1)/4-1 therefore, the ratio of S(4) and S(2) becomes ∼2n +1. The number of more binary switches required to express a particular multi-bit digit is also important, as this relationship determines how the memory density is effectively increasing or ho
    • q-1-1)/4- 1, which implies that p∼2q.
  • 17
    • 43249094501 scopus 로고    scopus 로고
    • accessed March 2008
    • b) http://www.cpu-world.com/CPUs/CPU.html (accessed March 2008).


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.