Nonvolatile memory with multilevel switching: A basic model

Physical Review Letters

Volumn 92, Issue 17, 2004, Pages

  Rozenberg, M J ^a,b   Inoue, I H ^c   Sanchez M J ^b  

^a CENTRE DE PHYSIQUE THÉORIQUE   (France)

^b UNIVERSIDAD DE BUENOS AIRES   (Argentina)

^c NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRODES; HYSTERESIS; INTERFACES (MATERIALS); MOBILE TELECOMMUNICATION SYSTEMS; MONTE CARLO METHODS; NETWORK PROTOCOLS; PEROVSKITE; PHASE SEPARATION; PROBABILITY; RANDOM ACCESS STORAGE; SILVER; SWITCHING; TERNARY SYSTEMS;

MULTILEVEL SWITCHING; NONVOLATILE MEMORY (NVM); OVONIC UNIFIED MEMORY (OUM); RESISTANCE RANDOM ACCESS MEMORY (RRAM);

NONVOLATILE STORAGE;

EID: 2942548117     PISSN: 00319007     EISSN: None     Source Type: Journal    
DOI: 10.1103/PhysRevLett.92.178302     Document Type: Article

References (28)

1. S. R. Ovshinsky, Phys. Rev. Lett. 21, 1450 (1968).
2. K. Terabe et al., Appl. Phys. Lett. 80, 4009 (2002); T. Sakamoto et al., Appl. Phys. Lett. 82, 3032 (2003).
3. K. Terabe et al., Appl. Phys. Lett. 80, 4009 (2002); T. Sakamoto et al., Appl. Phys. Lett. 82, 3032 (2003).
4. L. Ma et al., Appl. Phys. Lett. 82, 1419 (2003).
5. N. Koshida, K. Ueno, and X. Sheng, J. Lumin. 80, 37 (1999).
6. Y. Watanabe, Phys. Rev. B 59, 11257 (1999).
7. A. Beck et al., Appl. Phys. Lett. 77, 139 (2000).
8. Y. Watanabe et al., Appl. Phys. Lett. 78, 3738 (2001).
9. A. Sawa et al. (unpublished).
10. S. Q. Liu, N. J. Wu, and A. Ignatiev, Appl. Phys. Lett. 76, 2749 (2000).
11. S. Q. Liu et al., in Growth, Evolution and Properties of Surfaces, Thin Films and Self-Organized Structures Symposium, MRS Symposia Proceedings No. 648 (Materials Research Society, Warrendale, PA, 2001), pp. P3.26.1-8.
12. W.W. Zhuang et al., in International Electron Devices Meeting, Technical Digest No. 02CH37358 (IEEE, Piscataway, NJ, 2002), pp. 193-196.
13. S.T. Hsu et al., in Non-Volatile Semiconductor Memory Workshop (IEEE, Piscataway, NJ, 2003), pp. 123-124.
14. A. Baikalov et al., Appl. Phys. Lett. 83, 957 (2003).
15. A. Odagawa et al. (unpublished).
16. A. Moreo et al., Science 283, 2034 (1999); E. Dagotto et al., Phys. Rep. 344, 1 (2001); E. Dagotto, Nanoscale Phase Separation and Colossal Magnetoresistance (Springer-Verlag, Berlin, 2002).
17. A. Moreo et al., Science 283, 2034 (1999); E. Dagotto et al., Phys. Rep. 344, 1 (2001); E. Dagotto, Nanoscale Phase Separation and Colossal Magnetoresistance (Springer-Verlag, Berlin, 2002).
18. A. Moreo et al., Science 283, 2034 (1999); E. Dagotto et al., Phys. Rep. 344, 1 (2001); E. Dagotto, Nanoscale Phase Separation and Colossal Magnetoresistance (Springer-Verlag, Berlin, 2002).
19. S. H. Pan et al., Nature (London) 413, 282 (2001).
20. S. M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981).
21. The opposite choice would also lead to switching and hysteretic behavior, but with qualitative differences with respect to the present case.
22. G.W. Dietz et al., J. Appl. Phys. 78, 6113 (1995).
23. 1 uot = 1 unit of time = 1 Monte Carlo step in which all domains are updated.
24. The noise in the current is due to the Poisson nature of the carrier transfer process, yielding current fluctuations that are similar to those experimentally observed.
25. We assume the positive (erase) voltage pulses to be 20% larger than the negative (write) ones. Thus, the occupations (Fig. 3) saturate only upon erase.
26. Under a different choice of tunneling amplitudes, we have found qualitatively different hysteresis cycles. For instance, we observed switching between two "inverse" diode states, but not between two Ohmic resistive states.
27. H.-M. Christen et al., Phys. Rev. B 49, 12095 (1994).
28. M. Imada, A. Fujimori, and Y. Tokura, Rev. Mod. Phys. 70, 1039 (1998).