Gaussian monocycle pulse transmitter using 0.18 μm CMOS technology with on-chip integrated antennas for inter-chip UWB communication

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 5, 2008, Pages 1303-1311

  Kikkawa, Takamaro ^a,b   Saha, Pran Kanai ^b   Sasaki, Nobuo ^b   Kimoto, Kentaro ^b  

^a IEEE

^b HIROSHIMA UNIVERSITY   (Japan)

Author keywords

Antenna; CMOS; Gaussian monocycle pulse; Transmitter; Ultra wideband (UWB)

Indexed keywords

ANTENNAS; CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; ELECTRIC POWER UTILIZATION;

GAUSSIAN MONOCYCLE PULSE; INTER-CHIP UWB COMMUNICATION;

PULSE TRANSFORMERS;

EID: 42649117170     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.916588     Document Type: Conference Paper

References (19)

1. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion implanted MOSFET's with very small physical, dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, Oct. 1974.
2. H. B. Bakoglu and J. D. Meindl, "Optimal, interconnection circuits for VLSI," IEEE Trans. Electron Devices, vol. ED-32, pp. 903-909, May 1985.
3. T. Kikkawa, S. Chikaki, R. Yagi, M. Shimoyama, Shishida, N. Fujii, K. Kohmura, H. Tanaka, T. Nakayama, S. Hishiya, T. Ono, T. Yamanishi, A. Ishikawa, H. Matsuo, Y. Seino, N. Hata, T. Yoshino, S. Takada, J. Kawahara, and K. Kinoshita, "Advanced scalable ultra-low-k/Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier," in IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, Dec. 5, 2005, pp. 99-102.
4. A. Iwata, M. Sasaki, T. Kikkawa, S. Kameda, H. Ando, K. Kimoto, D. Arizono, and H. Sunami, "A 3-D integration scheme utilizing wireless interconnections for implementing hyper brains," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 262-263.
5. K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27 Gb/s/pin 3 m.W/pin Wireless Superconnect (WSC) interface scheme," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2003, pp. 186-187.
6. M. C. F. Chang, I. Verbauwhede, C. Chien, Z. Xu, J. Kim, J. Ko, Q. Gu, and B. C. Lai, "Advanced RF/baseband interconnect schemes for inter-and intra-ULSI communications," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1271-1285, Jul. 2005.
7. N. Miura, D. Mizoguchi, M. Inoue, H. Tsuji, T. Sakurai, and T. Kuroda, "A 195 Gb/s 1.2 W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 264-265.
8. B. A. Floyd, C. M. Hung, and K. O. Kenneth, "A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
9. A. B. M. H. Rashid, S. Watanabe, and T. Kikkawa, "High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect," IEEE Electron Device Lett., vol. 23, no. 12, pp. 731-733, Dec. 2002.
10. S. Watanabe, A. B. M. H. Rashid, and T. Kikkawa, "Effect of high resistivity Si substrate on antenna transmission gain for on-chip wireless interconnects," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2297-2301, Apr. 2004.
11. T. Kikkawa, K. Kimoto, and S. Watanabe, "Ultra wideband characteristics of fractal, dipole antennas integrated on Si for ULSI wireless interconnects," IEEE Electron Device Lett., vol. 26, no. 10, pp. 767-769, Oct. 2005.
12. K. K. O, K. Kim, B. A. Floyd, J. L. Mehta, H. Yoon, C. M. Hung, D. Bravo, T. O. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. R. Bomstad, J. Branch, D. J. Yang, J. Bohorquez, E. Seok, L. Gao, A. Sugavanam, J. J. Lin, J. Chen, and J. E. Brewer, "On-chip antennas in silicon ICs and their application," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1312-1323, Jul. 2005.
13. K. Kimoto and T. Kikkawa, "Transmission characteristics of gaussian monocycle pulses for inter-chip wireless interconnections using integrated antennas," Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2756-2760, Apr. 2005.
14. J. Han and C. Nguyen, "A new ultra-wideband, ultra-short monocycle pulse generator with reduced ringing," IEEE Microw. Wireless Compon. Lett., vol. 12, no. 6, pp. 206-208, Jun. 2002.
15. P. K. Saha, N. Sasaki, and T. Kikkawa, "A CMOS monocycle pulse generation circuit in a ultra-wideband transmitter for intra/inter chip wireless interconnection," Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2104-2108, 2005.
16. N. Sasaki, P. K. Saha, and T. Kikkawa, "The development of UWB Gaussian monocycle pulse synchronization circuit based on 0.18 μm CMOS technology," in Extended Abstracts 4th Hiroshima Int. Workshop on Nanoetectronics for Tera-Bit Information Processing, Hiroshima, Japan, Sep. 2005, pp. 72-73.
17. P. K. Saha, N. Sasaki, and T. Kikkawa, "A single chip Gaussian monocycle pulse transmitter using 0.18 μm CMOS technology for intra/inter-chip UWB communication," in Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, Jun. 11-15, 2006, pp. 252-253.
18. S. Bagga, A. V. Vorobyov, S. A. P. Haddad, A. G. Yarovoy, W. A. Serdijn, and J. R. Long, "Codesign of an impulse generator and miniaturized antennas for IR-UWB," IEEE Trans. Microw. Theory Tech., vol. 54, no. 4, pt. 2, pp. 1656-1666, Jun. 2006.
19. L. Stoica, A. Rabbachin, and I. Oppermann, "A low-complexity non-coherent IR-UWB transceiver architecture with TOA estimation," IEEE Trans. Microw. Theory Tech., vol. 54, no. 4, pt. 2, pp. 1637-1646, Jun. 2006.