An analytical expression for drain saturation voltage of polycrystalline silicon thin-film transistors

IEEE Electron Device Letters

Volumn 29, Issue 4, 2008, Pages 357-359

  Hao, Hao ^a   Wang, Mingxiang ^a   Wong, Man ^b  

^a SOOCHOW UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Drain saturation voltage; Output characteristic; Polycrystalline silicon; Thin film transistors (TFTs)

Indexed keywords

DRAIN CURRENT; GATES (TRANSISTOR); GRAIN BOUNDARIES; HIGH TEMPERATURE EFFECTS; LOW TEMPERATURE EFFECTS; POLYSILICON;

ANALYTICAL EXPRESSION; BARRIER MODULATION; DRAIN SATURATION VOLTAGE; OUTPUT CHARACTERISTIC;

THIN FILM TRANSISTORS;

EID: 41749120315     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.917810     Document Type: Article

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