Estimating error rate in defective logic using signature analysis

IEEE Transactions on Computers

Volumn 56, Issue 5, 2007, Pages 650-661

  Pan, Zhaoliang ^a   Breuer, Melvin A ^a  

^a University of Southern California   (United States)

Author keywords

Binning integrated circuits; Effective yield; Error rate; Error tolerance; Signature testing; Yield loss

Indexed keywords

BUILT-IN SELF TEST; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

ACCEPTABLE PERFORMANCE; CLASSIFICATION CRITERION; EFFECTIVE YIELD; ERROR RATE; ERROR TOLERANCE; MOLECULAR DIMENSIONS; VLSI MANUFACTURING; YIELD LOSS;

TESTING;

EID: 41449108810     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.1017     Document Type: Article

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