BEOL yield predictions for SIA roadmap

IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop

Volumn , Issue , 1997, Pages 87-90

  Chan, Luis ^a   Geuskens, Bibiche ^a   Mangaser, Ramon ^a   Rose, Kenneth ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; DEFECTS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PERFORMANCE; SYSTEMS ANALYSIS;

DEFECT DENSITY; INTERCONNECT RELATED EFFECTS; RENSSELAER INTERCONNECT PERFORMANCE ESTIMATOR; WIRING STRATEGY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0031368203     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)