Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

Solid-State Electronics

Volumn 52, Issue 4, 2008, Pages 564-570

  Zhang, Lu ^a   He, Wei ^a   Chan, Daniel S H ^a   Cho, Byung Jin ^a,b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Barrier structure; Floating gate; High material; Interfacial layer; Interpoly dielectric; Leakage current

Indexed keywords

ELECTRON TUNNELING; GATE DIELECTRICS; LEAKAGE CURRENTS; MULTILAYERS; POLYSILICON;

BARRIER STRUCTURE; INTERFACIAL LAYERS; INTERPOLY DIELECTRIC (IPD);

FLASH MEMORY;

EID: 40849140503     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.01.010     Document Type: Article

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