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Volumn 31, Issue 1, 2008, Pages 39-43

Advanced packaging: The redistributed chip package

Author keywords

Advanced packaging; Dielectric material; Electronic packaging; Redistribution

Indexed keywords

BALL GRID ARRAYS; COST REDUCTION; DIELECTRIC MATERIALS; EMBEDDED SYSTEMS; ENCAPSULATION; FLIP CHIP DEVICES;

EID: 40549125348     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.909456     Document Type: Article
Times cited : (39)

References (9)
  • 1
    • 33845571094 scopus 로고    scopus 로고
    • M. Brunnbauer, E. Fürgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomural, K. Kiuchi2, and K. Kobayashi, An embedded device technology based on a molded reconfigured wafer, in Proc. ECTC, 2006, p. 547.
    • M. Brunnbauer, E. Fürgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomural, K. Kiuchi2, and K. Kobayashi, "An embedded device technology based on a molded reconfigured wafer," in Proc. ECTC, 2006, p. 547.
  • 4
    • 0035555479 scopus 로고    scopus 로고
    • Novel microelectronic packaging method for reduced thermomechanical stresses on low dielectric constant materials
    • R. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, and G. J. Vandentop, "Novel microelectronic packaging method for reduced thermomechanical stresses on low dielectric constant materials," in Proc. Adv. Metallization Conf., 2001, p. 143.
    • (2001) Proc. Adv. Metallization Conf , pp. 143
    • Emery, R.1    Towle, S.2    Braunisch, H.3    Hu, C.4    Raiser, G.5    Vandentop, G.J.6
  • 5
    • 33845582061 scopus 로고    scopus 로고
    • Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP
    • C.-T. Ko, S. Chen, C.-W. Chiang, T.-Y. Kuo, Y.-C. Shih, and Y.-H. Chen, "Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP," in Proc. ECTC, 2006, p. 322.
    • (2006) Proc. ECTC , pp. 322
    • Ko, C.-T.1    Chen, S.2    Chiang, C.-W.3    Kuo, T.-Y.4    Shih, Y.-C.5    Chen, Y.-H.6
  • 6
    • 40549111923 scopus 로고    scopus 로고
    • Method for fabricating integrated circuit module, U.S. patent 5,353,498, 1994
    • "Method for fabricating integrated circuit module," U.S. patent 5,353,498, 1994.
  • 8
    • 35348893145 scopus 로고    scopus 로고
    • Technical understanding of resin coated copper lamination processes for realization of reliable chip embedding technologies
    • D. Manessis, H. Reichl, S. F. Yen, A. Ostermann, and R. Aschenbrenner, "Technical understanding of resin coated copper lamination processes for realization of reliable chip embedding technologies," in Proc. ECTC, 2007, p. 278.
    • (2007) Proc. ECTC , pp. 278
    • Manessis, D.1    Reichl, H.2    Yen, S.F.3    Ostermann, A.4    Aschenbrenner, R.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.