High I/O BGA packaging using chips first build-up

Proceedings - 2005 International Symposium on Microelectronics, IMAPS 2005

Volumn , Issue , 2005, Pages 619-624

  Fillion, Ray ^a   Burdick, William E ^a   Woychik, Charles ^a   Bauer, Charles E ^b   Neuhaus, Herbert J ^b  

^a GE GLOBAL RESEARCH   (United States)

^b TechLead Corp   (United States)

Author keywords

Build up BGA; Chips first; High I O count

Indexed keywords

BUILD-UP BGA; CHIPS FIRST; ELECTRICAL PERFORMANCE; FLIP CHIP SOLDER BUMP; HIGH I/O COUNT; HIGH-END MICROPROCESSORS; INTERCONNECT STRUCTURES; PACKAGING TECHNOLOGIES;

MICROELECTRONICS; TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 33947421242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. "Moore's Law" Intel.com web site.
2. Mahajan, R., Brown, K., Atluri, V., "The Evolution of Microprocessor Packaging," Intel Technology Journal, Vol. 6, #2, May 2002.
3. International Technology Roadmap for Semiconductors, 2001.
4. Banerjee, K. "Microprocessor Packaging," Intel Developer Forum, Fall 2001
5. TechLead Corp.