Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 8, 2004, Pages 793-811

  Pop, Paul ^a   Eles, Petru ^a   Peng, Zebo ^a   Pop, Traian ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Distributed embedded systems; Incremental design; Process mapping; Process scheduling; Real time systems

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; LINEAR PROGRAMMING; PROBLEM SOLVING; REAL TIME SYSTEMS; ROBOTICS; TELECOMMUNICATION; TIME DIVISION MULTIPLE ACCESS;

INCREMENTAL DESIGN; PROCESS MAPPING; PROCESS SCHEDULING; RUNNING SYSTEMS;

EMBEDDED SYSTEMS;

EID: 4043109846     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.831467     Document Type: Article

References (44)

1. J. E. Beck and D. P. Siewiorek, "Automatic configuration of embedded multicomputer systems," IEEE Trans. Computer-Aided Design, vol. 17, pp. 84-95, Feb. 1998.
2. T. Blicke, J. Teich, and L. Thiele, "System-level synthesis using evolutionary algorithms," Des. Autom. Embedded Syst., vol. 4, no. 1, pp. 23-58, 1998.
3. B. W. Boehm et al., Software Cost Estimation With COCOMO II. Englewood Cliffs, NJ: Prentice-Hall, 2000.
4. E. G. Coffman Jr. and R. L. Graham, "Optimal scheduling for two processor systems," Acta Informatica, no. 1, pp. 200-213, 1972.
5. B. P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems," IEEE Trans. VLSI Syst., vol. 7, pp. 92-104, Mar. 1999.
6. J. A. Debardelaben, V. K. Madiseti, and A. J. Gadient, "Incorporating cost modeling in embedded-system design," IEEE Des. Test Comput., pp. 24-35, July-Sept. 1997.
7. P. Eles, Z. Peng, K. Kuchcinski, and A. Doboli, "System level hardware/software partitioning based on simulated annealing and tabu search," Des. Autom. Embedded Syst., vol. 2, no. 1, pp. 5-32, 1997.
8. P. Eles, A. Doboli, P. Pop, and Z. Peng, "Scheduling with bus access optimization for distributed embedded systems," IEEE Trans. VLSI Syst., vol. 8, pp. 472-491, Oct. 2000.
9. R. Ernst, J. Henkel, and T. Benner, "Hardware-software cosynthesis for microcontrollers," IEEE Des. Test Comput., vol. 10, pp. 64-75, Sept. 1993.
10. R. Ernst, "Codesign of embedded systems: status and trends," IEEE Des. Test Comput., pp. 45-54, Apr.-June 1998.
11. D. D. Gajski and F. Vahid, "Specification and design of embedded hardware-software systems," IEEE Des. Test Comput., pp. 53-67, Spring 1995.
12. R. K. Gupta and G. De Micheli, "Hardware-software cosynthesis for digital systems," IEEE Des. Test Comput., vol. 10, pp. 29-41, Sept. 1993.
13. P. B. Jorgensen and J. Madsen, "Critical path driven cosynthesis for heterogeneous target architectures," in Proc. Int. Workshop on Hardware-Software Co-Design, 1997, pp. 15-19.
14. C. Haubelt, J. Teich, K. Richter, and R. Ernst, "System design for flexibility," in Proc. Design, Automation and Test Eur. Conf., 2002, pp. 854-861.
15. A. Kalawade and E. A. Lee, "The extended partitioning problem: hardware/software mapping, scheduling, and implementation-bin selection," Des. Autom. Embedded Syst., vol. 2, pp. 125-163, 1997.
16. P. V. Knudsen and J. Madsen, "Integrating communication protocol selection with hardware/software codesign," IEEE Trans. Computer-Aided Design, vol. 18, no. 8, pp. 1077-1095, 1999.
17. H. Kopetz, Real-Time Systems-Design Principles for Distributed Embedded Applications. Norwell, MA: Kluwer, 1997.
18. H. Kopetz and G. Grünsteidl, "TTP-a protocol for fault-tolerant realtime systems," IEEE Comput., vol. 27, pp. 14-23, Jan. 1994.
19. K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli, "System-level design: orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design, vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
20. C. Lee, M. Potkonjak, and W. Wolf, "Synthesis of hard real-time application specific systems," Des. Autom. Embedded Syst., vol. 4, no. 4, pp. 215-241, 1999.
21. Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, "Hardware-software co-design of embedded reconfigurable architectures," in Proc. Design Automation Conf., 2000, pp. 507-512.
22. S. Martello and P. Toth, Kanpsack Problems: Algorithms and Computer Implementations. New York: Wiley, 1990.
23. G. Martin and F. Schirrmeister, "A design chain for embedded systems," Computer, vol. 35, no. 3, pp. 100-103, Mar. 2002.
24. G. De Micheli and M. G. Sami, Eds., Hardware/Software Co-Design. Norwell, MA: Kluwer, 1996.
25. G. De Micheli and R. K. Gupta, "Hardware/software co-design," Proc. IEEE, vol. 85, pp. 349-365, 1997.
26. S. Narayan and D. D. Gajski, "Synthesis of system-level bus interfaces," in Proc. Eur. Desing and Test Conf., 1994, pp. 395-399.
27. R. B. Ortega and G. Borriello, "Communication synthesis for distributed embedded systems," in Proc. Int. Conf. CAD, 1998, pp. 437-444.
28. P. Pop, "Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems," Ph.D. dissertation, Linköping Studies in Science and Technology, Linköping, Sweden.
29. P. Pop, P. Eles, and Z. Peng, "Flexibility driven scheduling and mapping for distributed real-time systems," in Proc. Int. Conf. Real-Time Computing Systems and Applications, 2002, pp. 337-346.
30. _, "Scheduling with optimized communication for time-triggered embedded systems," in Proc. Int. Workshop on Hardware-Software Co-Design, 1999, pp. 178-182.
31. P. Pop, P. Eles, T. Pop, and Z. Peng, "An approach to incremental design of distributed embedded systems," in Proc. Design Automation Conf., 2001, pp. 450-455.
32. _, "Minimizing system modification in an incremental design approach," in Proc. Int. Workshop on Hardware/Software Codesign, 2001, pp. 183-188.
33. S. Prakash and A. Parker, "SOS: synthesis of application-specific heterogeneous multiprocessor systems," J. Parallel Distrib. Comput., vol. V16, pp. 338-351, 1992.
34. P. Puschner and A. Burns, "A review of worst-case execution-time analyzes," Real-Time Syst. J., vol. 18, no. 2/3, pp. 115-128, May 2000.
35. D. Ragan, P. Sandborn, and P. Stoaks, "A detailed cost model for concurrent use with hardware/software co-design," in Proc. Design Automation Conf., 2002, pp. 269-274.
36. C. R. Reevs, Modern Heuristic Techniques for Combinatorial Problems. Oxford, U.K: Blackwell, 1993.
37. D. L. Rhodes and W. Wolf, "Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication," in Proc. Int. Conf. CAD, 1999, pp. 339-342.
38. A. Sangiovanni-Vincentelli, "Electronic-system design in the automobile industry," IEEE Micro, vol. 23, pp. 8-18, May-June 2003.
39. J. Staunstrup and W. Wolf, Eds., Hardware/Software Co-Design: Principles and Practice. Norwell, MA: Kluwer, 1997.
40. W. Wolf, "An architectural co-synthesis algorithm for distributed, embedded computing systems," IEEE Trans. VLSI Syst., pp. 218-229, June 1997.
41. T. Y. Yen and W. Wolf, Hardware-Software Co-Synthesis of Distributed Embedded Systems. Norwell, MA: Kluwer, 1997.
42. W. Wolf, "Hardware-software co-design of embedded systems," Proc. IEEE, vol. 82, no. 7, pp. 967-989, 1994.
43. REVIC Software Cost Estimating Model, User's Manual, V9.0-9.2, U.S. Air Force Analysis Agency, 1994.
44. SoftEST - Version 1.1, U.S. Air Force Analysis Agency, 1997.