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Volumn 21, Issue 3, 2008, Pages 175-183

An evolutionary algorithm-based approach to robust analog circuit design using constrained multi-objective optimization

Author keywords

Analog circuit design; Circuit sizing; Constrained optimization; Design for manufacturability; Design for yield; Evolutionary optimization; Genetic algorithms; Multi objective optimization; Population based algorithms

Indexed keywords

ANALOG CIRCUITS; COMPUTATIONAL METHODS; CONSTRAINED OPTIMIZATION; LOGIC DESIGN;

EID: 40249087351     PISSN: 09507051     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.knosys.2007.11.014     Document Type: Article
Times cited : (59)

References (26)
  • 1
    • 85165841913 scopus 로고    scopus 로고
    • S.K. Tiwary, P.K. Tiwary, R.A. Rutenbar, Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration, in: 43rd DAC, 2006, pp. 31-36.
    • S.K. Tiwary, P.K. Tiwary, R.A. Rutenbar, Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration, in: 43rd DAC, 2006, pp. 31-36.
  • 3
    • 35248888997 scopus 로고    scopus 로고
    • V. Cutello, G. Nicosia, M. Pavone, A hybrid immune algorithm with information gain for the graph coloring problem, in: Proc. GECCO'03, LNCS 2723, 2003, pp. 171-182.
    • V. Cutello, G. Nicosia, M. Pavone, A hybrid immune algorithm with information gain for the graph coloring problem, in: Proc. GECCO'03, LNCS 2723, 2003, pp. 171-182.
  • 5
    • 0042635761 scopus 로고    scopus 로고
    • P. Magarshack, P.G. Paulin, System-on-chip beyond the nanometer wall, in: 40th DAC, 2003, pp. 419-424.
    • P. Magarshack, P.G. Paulin, System-on-chip beyond the nanometer wall, in: 40th DAC, 2003, pp. 419-424.
  • 6
    • 0034846245 scopus 로고    scopus 로고
    • F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Graeb, K. Antreich, Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility guided search, in: 38th DAC, 2001, pp. 858-863.
    • F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Graeb, K. Antreich, Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility guided search, in: 38th DAC, 2001, pp. 858-863.
  • 9
    • 0023994941 scopus 로고
    • DELIGHT.SPICE: an optimization-based system for the design of integrated circuits
    • Nye W., Riley D.C., Sangiovanni-Vincentelli A., and Tits A.L. DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. IEEE Trans. CAD 7 4 (1988) 501-519
    • (1988) IEEE Trans. CAD , vol.7 , Issue.4 , pp. 501-519
    • Nye, W.1    Riley, D.C.2    Sangiovanni-Vincentelli, A.3    Tits, A.L.4
  • 10
  • 11
    • 24644471543 scopus 로고    scopus 로고
    • V. Cutello, G. Morelli, G. Nicosia, M. Pavone, Immune algorithms with aging operators for the string folding problem and the protein folding problem, in: Proc. EvoCop'05, LNCS 3448, 2005, pp. 80-90.
    • V. Cutello, G. Morelli, G. Nicosia, M. Pavone, Immune algorithms with aging operators for the string folding problem and the protein folding problem, in: Proc. EvoCop'05, LNCS 3448, 2005, pp. 80-90.
  • 12
    • 0036977739 scopus 로고    scopus 로고
    • A global optimization approach for the synchronous motors design by finite element analysis
    • Cirio L., Lucidi S., Parasiliti F., and Villani M. A global optimization approach for the synchronous motors design by finite element analysis. Int. J. Appl. Electromagn. Mech. 16 (2002) 13-27
    • (2002) Int. J. Appl. Electromagn. Mech. , vol.16 , pp. 13-27
    • Cirio, L.1    Lucidi, S.2    Parasiliti, F.3    Villani, M.4
  • 13
    • 33750366840 scopus 로고    scopus 로고
    • V. Cutello, G. Narzisi, G. Nicosia, M. Pavone, Real coded clonal selection algorithm for global numerical optimization using a new inversely proportional hypermutation operator, in: 21st ACM SAC, 2006, pp. 950-954.
    • V. Cutello, G. Narzisi, G. Nicosia, M. Pavone, Real coded clonal selection algorithm for global numerical optimization using a new inversely proportional hypermutation operator, in: 21st ACM SAC, 2006, pp. 950-954.
  • 14
    • 0035446066 scopus 로고    scopus 로고
    • A locally-biased form of the DIRECT algorithm
    • Gablonsky J.M., and Kelley C.T. A locally-biased form of the DIRECT algorithm. J. Global Optimization 21 (2001) 27-37
    • (2001) J. Global Optimization , vol.21 , pp. 27-37
    • Gablonsky, J.M.1    Kelley, C.T.2
  • 15
    • 33846538819 scopus 로고    scopus 로고
    • The NEWUOA software for unconstrained optimization without derivatives
    • Di Pillo G., and Roma M. (Eds), Springer, NY
    • Powell M.J.D. The NEWUOA software for unconstrained optimization without derivatives. In: Di Pillo G., and Roma M. (Eds). Large-Scale Nonlinear Optimization (2006), Springer, NY 255-297
    • (2006) Large-Scale Nonlinear Optimization , pp. 255-297
    • Powell, M.J.D.1
  • 17
    • 33746369469 scopus 로고    scopus 로고
    • Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    • Calhoun B.H., and Chandrakasan A.P. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J. Solid-State Circuits 41 (2006) 1673-1679
    • (2006) IEEE J. Solid-State Circuits , vol.41 , pp. 1673-1679
    • Calhoun, B.H.1    Chandrakasan, A.P.2
  • 18
    • 27944462775 scopus 로고    scopus 로고
    • N. Jayakumar, S.P. Khatri, A variation-tolerant sub-threshold design approach, in: 42nd DAC, 2005, pp. 716-719.
    • N. Jayakumar, S.P. Khatri, A variation-tolerant sub-threshold design approach, in: 42nd DAC, 2005, pp. 716-719.
  • 20
    • 34047174862 scopus 로고    scopus 로고
    • A. Raychowdhury, B.C. Paul, S. Bhunia, K. Roy, Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies, in: Proc. Conf. DATE, 2006, pp. 856-861.
    • A. Raychowdhury, B.C. Paul, S. Bhunia, K. Roy, Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies, in: Proc. Conf. DATE, 2006, pp. 856-861.
  • 21
    • 33846261495 scopus 로고    scopus 로고
    • Low-power design space exploration considering process variation using robust optimization
    • Srivastava A., Kachru T., and Sylvester D. Low-power design space exploration considering process variation using robust optimization. IEEE Trans. CAD 26 1 (2007) 67-79
    • (2007) IEEE Trans. CAD , vol.26 , Issue.1 , pp. 67-79
    • Srivastava, A.1    Kachru, T.2    Sylvester, D.3
  • 22
    • 16244376164 scopus 로고    scopus 로고
    • B.C. Paul, A. Raychowdhury, K. Roy, Device optimization for ultra-low power digital sub-threshold operation, in: Proc. 2004 Int. Symp. on Low Power Electronics and Design, 2004, pp. 96-101.
    • B.C. Paul, A. Raychowdhury, K. Roy, Device optimization for ultra-low power digital sub-threshold operation, in: Proc. 2004 Int. Symp. on Low Power Electronics and Design, 2004, pp. 96-101.
  • 23


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.