A 1.5 V 86 mW/ch 8-channel 622-3125 Mb/s/ch CMOS SerDes macrocell with selectable Mux/Demux ratio

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 68-69+445+67

  Yang, Fuji ^a   O'Neill, Jay ^a   Larsson, Patrik ^a   Inglis, Dave ^a   Othmer, Joe ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; INTERPOLATION; MULTIPLEXING; PHASE LOCKED LOOPS; PHASE SHIFT; THROUGHPUT; TIMING JITTER; TRANSCEIVERS; TRANSMITTERS;

DIFFERENTIAL CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0036116456     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver
2. An 84mW 4 Gb/s clock and data recovery circuit for serial link applications
3. A 700Mb/s/pin CMOS signaling interface using a current integrating receivers
4. A CMOS interface circuit for detection of 1.2 Gb/s RZ data
5. An offset-cancelled CMOS clock recovery/demux with half-rate linear phase detector for 2.5 Gb/s optical communication
6. A 2.5 V CMOS delay-locked loop for an 18 Mb, 500 Mb/s DRAM