0.13-μm low-κ-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel

IEEE Transactions on Electron Devices

Volumn 51, Issue 5, 2004, Pages 757-763

  Guo, Jyh Chyurn ^a   Lien, W Y ^b   Tsai, T L ^b   Chen, S M ^b   Wu, C M ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Dual gate oxide; High performance analog (HPA); Read channel

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROELECTRONIC PROCESSING; OXIDES; SPURIOUS SIGNAL NOISE;

DUAL GATE OXIDE; HIGH DATA RATE READ CHANNEL; HIGH PERFORMANCE ANALOG;

LOGIC DEVICES;

EID: 2442488954     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.826884     Document Type: Article

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