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Volumn , Issue , 2006, Pages 117-121

Impact of intrinsic parameter fluctuations on DECA-nanometer circuits, and circuit modelling techniques

Author keywords

Compact model; Intrinsic parameter fluctuations; SRAM; Statistical circuit simulation; Statistical device simulation

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION; RANDOM PROCESSES;

EID: 39549096827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (12)
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    • Intrinsic Parameter Fluctuations in Decananometer MOSFETs introduced by gate line edge roughness
    • A. Asenov et al, "Intrinsic Parameter Fluctuations in Decananometer MOSFETs introduced by gate line edge roughness", IEEE Trans. on Electron Devices, Vol. 50, pp. 1254-1260
    • IEEE Trans. on Electron Devices , vol.50 , pp. 1254-1260
    • Asenov, A.1
  • 2
    • 27944511578 scopus 로고    scopus 로고
    • CAD Tools for Variation Tolerance
    • D. Blaauw, K. Chopra, "CAD Tools for Variation Tolerance", Proc. DAC 2005, pp. 766
    • (2005) Proc. DAC , pp. 766
    • Blaauw, D.1    Chopra, K.2
  • 3
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    • http://public.itrs.net/
  • 4
    • 41549112351 scopus 로고    scopus 로고
    • Taurus User's manual, Synopsys, 2003
    • Taurus User's manual, Synopsys, 2003
  • 5
    • 0037004304 scopus 로고    scopus 로고
    • High performance 35nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
    • S. Inaba, K. Okano, S. Matsuda, et al., "High performance 35nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide", IEEE Trans on Electron Devices, vol. 49, pp. 2263-2270.
    • IEEE Trans on Electron Devices , vol.49 , pp. 2263-2270
    • Inaba, S.1    Okano, K.2    Matsuda, S.3
  • 6
    • 84948782220 scopus 로고    scopus 로고
    • Integrated atomistic process and device simulation of decananometre MOSFETs
    • A. A. Asenov, M. Jaraiz, S. Roy, G. Roy, et al., "Integrated atomistic process and device simulation of decananometre MOSFETs," Proc. SISPAD 2002, pp. 87-90
    • (2002) Proc. SISPAD , pp. 87-90
    • Asenov, A.A.1    Jaraiz, M.2    Roy, S.3    Roy, G.4
  • 7
    • 3242675991 scopus 로고    scopus 로고
    • Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulations
    • G. Roy, A. R. Brown, A. Asenov, and S. Roy, " Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulations," Superlattices and Microstructures, vol. 34, pp. 327-334
    • Superlattices and Microstructures , vol.34 , pp. 327-334
    • Roy, G.1    Brown, A.R.2    Asenov, A.3    Roy, S.4
  • 8
    • 41549163838 scopus 로고    scopus 로고
    • http://www.device.eecs.berkeley.edu/~bsim3
  • 9
    • 41549142165 scopus 로고    scopus 로고
    • Compact Model Strategy for Studying the Impact of Intrinsic Parameter Fluctuations on Circuit Peformance
    • B. Cheng, S. Roy, A. Asenov, "Compact Model Strategy for Studying the Impact of Intrinsic Parameter Fluctuations on Circuit Peformance", Proc. MIXDES 2004
    • (2004) Proc. MIXDES
    • Cheng, B.1    Roy, S.2    Asenov, A.3
  • 10
    • 17944400303 scopus 로고    scopus 로고
    • CMOS device optimisation for mixed-signal technologies
    • Stolk P A, Tuinhout H P, Duffy R, et al., "CMOS device optimisation for mixed-signal technologies", IEDM Tech. Digest 2001, pp. 215-218.
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  • 11
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    • Low Power, High Density CMOS 6-T SRAM Cell Design Subject to 'Atomistic' Fluctuations
    • B. Cheng, S. Roy, A. Asenov, "Low Power, High Density CMOS 6-T SRAM Cell Design Subject to 'Atomistic' Fluctuations", Proc. ULIS 2006.
    • (2006) Proc. ULIS
    • Cheng, B.1    Roy, S.2    Asenov, A.3
  • 12
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    • A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.