Design optimization of AlInAs-GaInAs HEMTs for low-noise applications

IEEE Transactions on Electron Devices

Volumn 51, Issue 8, 2004, Pages 1228-1233

  Mateos, Javier ^a   González, Tomás ^a   Pardo, Daniel ^a   Bollaert, Sylvain ^b   Parenty, Thierry ^b   Cappy, Alain ^b  

^a UNIVERSITY OF SALAMANCA   (Spain)

^b Institut d'Electronique   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DESIGN; ELECTRIC ADMITTANCE; ELECTRIC RESISTANCE; GAUSSIAN NOISE (ELECTRONIC); MONTE CARLO METHODS; OPTIMIZATION; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DOPING;

HIGH SPEED DEVICES; MINIMUM NOISE FIGURE; NOISE PARAMETERS; PARASITIC CAPACITANCE; PARASITIC RESISTANCES; SEMICONDUCTOR DEVICE DESIGN; SEMICONDUCTOR DEVICE FABRICATION;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 3943068446     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.832095     Document Type: Article

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