Design and realization of sub 100nm gate length HEMTs

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2001, Pages 626-629

  Parenty, T ^a   Bollaert, S ^a   Mateos, J ^a   Wallart, X ^a   Cappy, A ^a  

^a INSTITUT D ELECTRONIQUE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); MICROWAVE DEVICES; MONTE CARLO METHODS; OSCILLATIONS; SEMICONDUCTING INDIUM GALLIUM ARSENIDE;

GATE LENGTH;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0034841546     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. InP-based HEMT technologies for high-speed ICs
2. T 50-nm-gate lattice matched InAlAs/InGaAs HEMTs
3. max
4. Design optimisation of ultra-short gate HEMTs using Monte Carlo simulation