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Volumn , Issue , 2007, Pages 87-92

Energy efficient co-scheduling in dynamically reconfigurable systems

Author keywords

Energy efficient; Reconfigurable systems

Indexed keywords

COMPUTER HARDWARE; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; PROGRAM PROCESSORS; SCHEDULING;

EID: 38849157722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289840     Document Type: Conference Paper
Times cited : (6)

References (13)
  • 4
    • 84949777938 scopus 로고    scopus 로고
    • Configuration caching management techniques for reconfigurable computing
    • IEEE Computer Society Press, April
    • Z. Li, K. Compton, and S. Hauck. Configuration caching management techniques for reconfigurable computing. In Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 87-96. IEEE Computer Society Press, April 2000.
    • (2000) Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines , pp. 87-96
    • Li, Z.1    Compton, K.2    Hauck, S.3
  • 7
    • 16244395784 scopus 로고    scopus 로고
    • Configuration bitstream compression for dynamically reconfigurable FPGAs
    • IEEE Computer Society Press, November
    • J. H. Pan, T. M. Weng, and F. Wong. Configuration bitstream compression for dynamically reconfigurable FPGAs. In International Conference on Computer Aided Design (ICCAD), pages 766-773. IEEE Computer Society Press, November 2004.
    • (2004) International Conference on Computer Aided Design (ICCAD) , pp. 766-773
    • Pan, J.H.1    Weng, T.M.2    Wong, F.3
  • 8
    • 33646940730 scopus 로고    scopus 로고
    • A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware
    • IEEE Computer Society Press, March
    • J. Resano, D. Mozos, and F. Catthoor. A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware. In Proc. of the Conference on Design, Automation and Test in Europe, pages 106-111. IEEE Computer Society Press, March 2005.
    • (2005) Proc. of the Conference on Design, Automation and Test in Europe , pp. 106-111
    • Resano, J.1    Mozos, D.2    Catthoor, F.3
  • 9
  • 10
    • 21144456346 scopus 로고    scopus 로고
    • Run-time minimization of reconfiguration overhead in dynamically reconfigurable systems
    • Proc. of the 13th International Conference Field-Programmable Logic and Applications FPL, of, Springer Verlag, September
    • J. Resano, D. Mozos, D. Verkest, S. Vernalde, and F. Catthoor. Run-time minimization of reconfiguration overhead in dynamically reconfigurable systems. In Proc. of the 13th International Conference Field-Programmable Logic and Applications (FPL), volume 2778 of LNCS, pages 585-594. Springer Verlag, September 2003.
    • (2003) LNCS , vol.2778 , pp. 585-594
    • Resano, J.1    Mozos, D.2    Verkest, D.3    Vernalde, S.4    Catthoor, F.5
  • 12
    • 84962312624 scopus 로고    scopus 로고
    • Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs
    • IEEE Computer Society Press, January
    • L. Shang and N. K. Jha. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs. In Proc. of the International Conference on VLSI Design, pages 345-352. IEEE Computer Society Press, January 2002.
    • (2002) Proc. of the International Conference on VLSI Design , pp. 345-352
    • Shang, L.1    Jha, N.K.2
  • 13
    • 84997196860 scopus 로고    scopus 로고
    • Blocking-aware processor voltage scheduling for real-time tasks
    • May
    • F. Zhang and S. T. Chanson. Blocking-aware processor voltage scheduling for real-time tasks. A CM Transactions on Embedded Computing Systems, 3(2):307-335, May 2004.
    • (2004) A CM Transactions on Embedded Computing Systems , vol.3 , Issue.2 , pp. 307-335
    • Zhang, F.1    Chanson, S.T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.