-
1
-
-
0030171884
-
Architecture of fpgas and clpds: A tutorial
-
S. Brown, J. Rose. Architecture of FPGAs and CLPDs: A Tutorial, IEEE Design and Test of Computer, Vol. 13, No 2, pp. 42-57, 1996
-
(1996)
IEEE Design and Test of Computer
, vol.13
, Issue.2
, pp. 42-57
-
-
Brown, S.1
Rose, J.2
-
2
-
-
0011493977
-
A first generation dpga implementation
-
May 29-Jun 1
-
E. Tau, D. Chen, I. Eslick, J. Brown and A. De Hon, A First Generation DPGA Implementation, FDP?95, Canadian Workshop of Field-Programmable Devices, May 29-Jun 1, 1995
-
(1995)
FDP?95, Canadian Workshop of Field-Programmable Devices
-
-
Tau, E.1
Chen, D.2
Eslick, I.3
Brown, J.4
De Hon, A.5
-
3
-
-
0034187952
-
Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications
-
May
-
H. Singh, M. Lee, G. Lu, F. Kurdahi, et al,-MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications, IEEE Transactions on Computers, pp. 465-481, Vol. 49, No. 5, May, 2000
-
(2000)
IEEE Transactions on Computers
, vol.49
, Issue.5
, pp. 465-481
-
-
Singh, H.1
Lee, M.2
Lu, G.3
Kurdahi, F.4
-
4
-
-
84963548486
-
Parallel volume rendering on a single-chip simd architercture
-
San Diego, Ca October
-
M. Meiner, S.Grimm, W. Straer, et al, Parallel Volume Rendering on a Single-Chip SIMD Architercture, IEEE Symposium on Parallel and Large-Data Visuallization and Graphics, San Diego, Ca, October, 2001
-
(2001)
IEEE Symposium on Parallel and Large-Data Visuallization and Graphics
-
-
Meiner, M.1
Grimm, S.2
Straer, W.3
-
5
-
-
0034818451
-
A study of memory system performance of multimedia applications
-
S. Sohoni, R. Min, Z. Xu, Y. Hu. A study of memory system performance of multimedia applications, SIGMETRICS Performance 2001, pp. 206-215
-
(2001)
SIGMETRICS Performance
, pp. 206-215
-
-
Sohoni, S.1
Min, R.2
Xu, Z.3
Hu, Y.4
-
6
-
-
1142271379
-
Kernel scheduling in reconfigurables architectures
-
R. Maestre, F. Kurdahi, et al. Kernel Scheduling in Reconfigurables Architectures, DATE Proceedings pp 90-96, 1999
-
(1999)
DATE Proceedings
, pp. 90-96
-
-
Maestre, R.1
Kurdahi, F.2
-
7
-
-
2642571809
-
Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations
-
20-22 September
-
R. Maestre, F. J. Kurdahi, M. Fernandez, et al. Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimizations, ISSS Proceedings, pp. 107-113, 20-22 September 2000
-
(2000)
ISSS Proceedings
, pp. 107-113
-
-
Maestre, R.1
Kurdahi, F.J.2
Fernandez, M.3
-
8
-
-
16244402577
-
A complete data scheduler for multi-context reconfigurable architectures
-
Paris, France 547-552 March 2002
-
M. Sanchez-Elez, M. Fernández, et al. A Complete Data Scheduler for Multi-Context Reconfigurable Architectures DATE Proceedings, Paris, France, pp. 547-552 March 2002
-
DATE Proceedings
-
-
Sanchez-Elez, M.1
Fernández, M.2
-
9
-
-
33746967016
-
Data and memory optimization techniques for embedded systems
-
Apr
-
Panda, P., R. Catthoor, F., Dutt, N. D., Danckaert et al. Data and Memory Optimization Techniques for Embedded Systems, ACM Transactions on Design Automation of Electronic Systems. Vol. 6, Iss. 2. Apr. 2001
-
(2001)
ACM Transactions on Design Automation of Electronic Systems
, vol.6
, Issue.2
-
-
Panda, P.1
Catthoor, R.2
Dutt, F.3
Danckaert, N.D.4
-
10
-
-
0001868375
-
Global communication and memory optimizing transformations for low power design
-
Napa Valley, CA Apr
-
S. Wuytack, F. Catthoor, et al. Global communication and memory optimizing transformations for low power design, in Proc. IWLPD-94: Int. Workshop on Low Power Design, Napa Valley, CA, Apr. 1994, pp. 203-208
-
(1994)
Proc. IWLPD-94: Int. Workshop on Low Power Design
, pp. 203-208
-
-
Wuytack, S.1
Catthoor, F.2
-
11
-
-
0032681537
-
An automated temporal partitioning and loop fission approach for fpga based reconfigurable synthesis of dsp applications
-
M. Kaul, R. Vemuri, et al. An Automated Temporal Partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications Proc. 36th Design automation conference, 1999, Pages 616-622
-
(1999)
Proc. 36th Design Automation Conference
, pp. 616-622
-
-
Kaul, M.1
Vemuri, R.2
-
12
-
-
0028712353
-
Hardaware-software partitioning and minimizing memory interface traffic
-
A. Jantsch, P. Ellervee, A. Hemani, et al. Hardaware-Software Partitioning and Minimizing Memory Interface Traffic, DATE Proceedings, 1994, Pages 226-231
-
(1994)
DATE Proceedings
, pp. 226-231
-
-
Jantsch, A.1
Ellervee, P.2
Hemani, A.3
-
13
-
-
84958662213
-
Dynamic storage application a survey and critical review
-
P.R. Wilson, M.S. Johnstone, M Neely, and D Boles Dynamic Storage Application A Survey and Critical Review IWMM 1995: 1-116
-
(1995)
IWMM
, pp. 1-116
-
-
Wilson, P.R.1
Johnstone, M.S.2
Neely, M.3
Boles, D.4
-
14
-
-
33845302760
-
Analytical energy dissipation models for low power caches
-
Research triangle Park, NC December
-
M. B. Kamble and K. Ghose, Analytical Energy Dissipation Models for Low Power Caches, ACM/IEEE International Symposium on Microarchitecture, pp 184-193, Research triangle Park, NC, December 1997
-
(1997)
ACM/ IEEE International Symposium on Microarchitecture
, pp. 184-193
-
-
Kamble, M.B.1
Ghose, K.2
-
15
-
-
0031336708
-
The filter cache: An energy efficient memory structure
-
Research Triangle Park, NC December
-
J. Kin, M. Gupta and W. H. Mangione-Smith, The Filter Cache: An Energy Efficient Memory Structure, MICRO-97: International Symposium on Microarchitecture, pp 184-193, Research Triangle Park, NC, December 1997
-
(1997)
MICRO-97: International Symposium on Microarchitecture
, pp. 184-193
-
-
Kin, J.1
Gupta, M.2
Mangione-Smith, W.H.3
-
16
-
-
0242357904
-
Low power techniques for address encoding and memory allocation
-
Jan
-
W. Cheng, M. Pedram, Low Power Techniques for Address Encoding and Memory Allocation, Procc. of Asia and South Pacific DAC, Jan. 2001, pp. 245-250
-
(2001)
Procc. of Asia and South Pacific DAC
, pp. 245-250
-
-
Cheng, W.1
Pedram, M.2
-
17
-
-
84893785531
-
-
Low Power Workshop, Ulm, Germany, Sep.?94
-
P. Van Oostende, G. Van Wauve, Low Power design: A gated-clock strategy Low Power Workshop, Ulm, Germany, Sep.?94
-
Low Power Design: A Gated-clock Strategy
-
-
Van Oostende, P.1
Van Wauve, G.2
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