System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2003, Pages 73-83

  Noguera, Juanjo ^a   Badia, Rosa M ^b  

^a Research and Development Dept   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Clock gating; Dynamic scheduling; Frequency scaling; Power performance trade offs; Reconfigurable Computing

Indexed keywords

ALGORITHMS; COMPUTER OPERATING SYSTEMS; ELECTRIC CLOCKS; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; PERFORMANCE; SCHEDULING; SUPERVISORY AND EXECUTIVE PROGRAMS; SYSTEMS ANALYSIS;

CLOCK-GATING; DYNAMIC SCHEDULING; FREQUENCY SCALING; POWER-PERFORMANCE TRADE-OFFS; RECONFIGURABLE COMPUTING;

COMPUTER ARCHITECTURE;

EID: 16244410003     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/951710.951722     Document Type: Conference Paper

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