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Volumn 2778, Issue , 2003, Pages 585-594

Run-time minimization of reconfiguration overhead in dynamically reconfigurable systems

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; ENERGY UTILIZATION; RECONFIGURABLE HARDWARE;

EID: 21144456346     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_57     Document Type: Article
Times cited : (21)

References (11)
  • 1
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    • Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimizations
    • R. Maestre et al., "Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimizations", ISSS'00, pp 107-113, 2000.
    • (2000) ISSS'00 , pp. 107-113
    • Maestre, R.1
  • 2
    • 35248889947 scopus 로고    scopus 로고
    • Low-Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures
    • M. Sánchez-Elez et al "Low-Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures". DATE'03, pp. 36-41, 2003.
    • (2003) DATE'03 , pp. 36-41
    • Sánchez-Elez, M.1
  • 3
    • 0035341757 scopus 로고    scopus 로고
    • Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
    • M. Wan et al. "Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System", Journal of VLSI Signal Processing 28, pp. 47-61, 2001.
    • (2001) Journal of VLSI Signal Processing , vol.28 , pp. 47-61
    • Wan, M.1
  • 4
    • 84961879697 scopus 로고    scopus 로고
    • Reducing the power Consumption in FPGAs with keeping a high Performance Level
    • A. D. Garcia et al., "Reducing the power Consumption in FPGAs with keeping a high Performance Level", WVLSI00, pp 47-52, 2002.
    • (2002) WVLSI00 , pp. 47-52
    • Garcia, A.D.1
  • 5
    • 84962312624 scopus 로고    scopus 로고
    • Hw/Sw Co-synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs
    • Li Shang et al., "Hw/Sw Co-synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs", ASP-DAC'02, pp. 345-360, 2002.
    • (2002) ASP-DAC'02 , pp. 345-360
    • Shang, L.1
  • 6
    • 79955158088 scopus 로고    scopus 로고
    • Interconnection Network enable Fine-Grain Dynamic Multi-Tasking on FPGAs
    • T. Marescaux et al.,"Interconnection Network enable Fine-Grain Dynamic Multi-Tasking on FPGAs", FPL'02, pp. 795-805, 2002.
    • (2002) FPL'02 , pp. 795-805
    • Marescaux, T.1
  • 7
    • 0035444245 scopus 로고    scopus 로고
    • Energy-Aware Runtime Scheduling for Embedded-Multiprocessors SOCs
    • P. Yang et al., "Energy-Aware Runtime Scheduling for Embedded-Multiprocessors SOCs", IEEE Journal on Design&Test of Computers, pp. 46-58, 2001.
    • (2001) IEEE Journal on Design&Test of Computers , pp. 46-58
    • Yang, P.1
  • 8
    • 0347934778 scopus 로고    scopus 로고
    • Matador, an Exploration Environment for System-Design
    • P. Marchai et al, "Matador, an Exploration Environment for System-Design", Journal of Circuits, Systems and Computers, Vol. 11, No. 5, pp. 503-535, 2002.
    • (2002) Journal of Circuits, Systems and Computers , vol.11 , Issue.5 , pp. 503-535
    • Marchai, P.1
  • 9
    • 0036957555 scopus 로고    scopus 로고
    • Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia systems
    • P. Yang et al, "Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia systems", ISSS'02, pp. 112-119, 2002.
    • (2002) ISSS'02 , pp. 112-119
    • Yang, P.1
  • 10
    • 0036382691 scopus 로고    scopus 로고
    • Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation
    • Z. Li and S. Hauck, "Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation" Int'l Symp. FPGAs, pp. 187-195, 2002.
    • (2002) Int'l Symp. FPGAs , pp. 187-195
    • Li, Z.1    Hauck, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.