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Volumn 129, Issue 3, 2007, Pages 307-315

Simulations of process-induced warpage during IC encapsulation process

Author keywords

Cure induced shrinkage; IC package; P V T C equation; Warpage

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; ENCAPSULATION; OPTIMIZATION; PROBLEM SOLVING; SHRINKAGE;

EID: 38749145161     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2753936     Document Type: Article
Times cited : (13)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.