System architecture and implementation of MIMO sphere decoders on FPGA

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 2, 2008, Pages 188-196

  Huang, Xinming ^a,b   Liang, Cao ^a,b   Ma, Jing ^a,c,d  

^a IEEE

^b WORCESTER POLYTECHNIC INSTITUTE   (United States)

^c UNO College of Engineering   (United States)

^d MATHWORKS INC   (United States)

Author keywords

Field programmable gate array (FPGA); Lattice point search; Multiple input multiple output (MIMO) detection; Parallel structure; Sphere decoding; System on chip (SoC)

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); TRANSMITTERS;

LATTICE POINT SEARCH; SPHERE DECODING;

DECODING;

EID: 38349127026     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.912042     Document Type: Article

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