-
1
-
-
0003073668
-
Vectorized mixed radix discrete Fourier transform algorithms
-
Agarwal, R.C., Cooley, J.W.: Vectorized mixed radix discrete Fourier transform algorithms. Proc. of the IEEE 75(9), 1283-1292 (1987)
-
(1987)
Proc. of the IEEE
, vol.75
, Issue.9
, pp. 1283-1292
-
-
Agarwal, R.C.1
Cooley, J.W.2
-
2
-
-
0023965239
-
A segmented FFT algorithm for vector computers
-
Ashworth, M., Lyne, A.G.: A segmented FFT algorithm for vector computers. Parallel Computing 6(2), 217-224 (1988)
-
(1988)
Parallel Computing
, vol.6
, Issue.2
, pp. 217-224
-
-
Ashworth, M.1
Lyne, A.G.2
-
3
-
-
0025491614
-
A parallel FFT on an MIMD machine
-
Averbuch, A., Gabber, E., Gordissky, B., Medan, Y.: A parallel FFT on an MIMD machine. Parallel Computing 15, 61-74 (1990)
-
(1990)
Parallel Computing
, vol.15
, pp. 61-74
-
-
Averbuch, A.1
Gabber, E.2
Gordissky, B.3
Medan, Y.4
-
4
-
-
84972625237
-
A high-performance FFT algorithm for vector supercomputers
-
Bailey, D.H.: A high-performance FFT algorithm for vector supercomputers. Intl. Journal of Supercomputer Applications 2(1), 82-87 (1988)
-
(1988)
Intl. Journal of Supercomputer Applications
, vol.2
, Issue.1
, pp. 82-87
-
-
Bailey, D.H.1
-
5
-
-
34548753903
-
Cell Broadband Engine Architecture and its first implementation
-
Technical Report November
-
Chen, T., Raghavan, R., Dale, J., Iwata, E.: Cell Broadband Engine Architecture and its first implementation. Technical Report (November 2005)
-
(2005)
-
-
Chen, T.1
Raghavan, R.2
Dale, J.3
Iwata, E.4
-
9
-
-
34147099975
-
-
IBM Corporation, at IBM Research
-
IBM Corporation. The Cell project at IBM Research, http://www.research. ibm.com/cell/home.html
-
The Cell project
-
-
-
10
-
-
27644524078
-
A streaming processor unit for a Cell processor
-
San Fransisco, CA, USA, February
-
Flachs, B., et al.: A streaming processor unit for a Cell processor. In: International Solid State Circuits Conference, San Fransisco, CA, USA, vol. 1, pp. 134-135 (February 2005)
-
(2005)
International Solid State Circuits Conference
, vol.1
, pp. 134-135
-
-
Flachs, B.1
-
12
-
-
38349055295
-
Cell Broadband Engine Architecture from 20,000 feet
-
Technical Report August
-
Hofstee, H.P.: Cell Broadband Engine Architecture from 20,000 feet. Technical Report (August 2005)
-
(2005)
-
-
Hofstee, H.P.1
-
13
-
-
51049096049
-
Real-time supercomputing and technology for games and entertainment (keynote talk)
-
Hofstee, H.P.: Real-time supercomputing and technology for games and entertainment (keynote talk). In: Proc. SC, Tampa, FL (November 2006)
-
(2006)
Proc. SC, Tampa, FL (November
-
-
Hofstee, H.P.1
-
14
-
-
27944446098
-
The vector floating-point unit in a synergistic processor element of a Cell processor
-
Washington, DC, USA, pp, IEEE Computer Society Press, Los Alamitos
-
Jacobi, C., Oh, H.-J., Tran, K.D., Cottier, S.R., Michael, B.W., Nishikawa, H., Totsuka, Y., Namatame, T., Yano, N.: The vector floating-point unit in a synergistic processor element of a Cell processor. In: Proc. 17th IEEE Symposium on Computer Arithmetic (ARITH 2005), Washington, DC, USA, pp. 59-67. IEEE Computer Society Press, Los Alamitos (2005)
-
(2005)
Proc. 17th IEEE Symposium on Computer Arithmetic (ARITH
, pp. 59-67
-
-
Jacobi, C.1
Oh, H.-J.2
Tran, K.D.3
Cottier, S.R.4
Michael, B.W.5
Nishikawa, H.6
Totsuka, Y.7
Namatame, T.8
Yano, N.9
-
15
-
-
25844503119
-
Introduction to the Cell multiprocessor
-
Kahle, J.A., Day, M.N., Hofstee, H.P., Johns, C.R., Maeurer, T.R., Shippy, D.: Introduction to the Cell multiprocessor. IBM J. Res. Dev. 49(4/5), 589-604 (2005)
-
(2005)
IBM J. Res. Dev
, vol.49
, Issue.4-5
, pp. 589-604
-
-
Kahle, J.A.1
Day, M.N.2
Hofstee, H.P.3
Johns, C.R.4
Maeurer, T.R.5
Shippy, D.6
-
16
-
-
33746923043
-
Cell multiprocessor communication network: Built for speed
-
Kistler, M., Perrone, M., Petrini, F.: Cell multiprocessor communication network: Built for speed. IEEE Micro 26(3), 10-23 (2006)
-
(2006)
IEEE Micro
, vol.26
, Issue.3
, pp. 10-23
-
-
Kistler, M.1
Perrone, M.2
Petrini, F.3
-
17
-
-
27344435504
-
The design and implementation of a first-generation Cell processor
-
San Fransisco, CA, USA, February
-
Pham, D., et al.: The design and implementation of a first-generation Cell processor. In: International Solid State Circuits Conference, San Fransisco, CA, USA, vol. 1, pp. 184-185 (February 2005)
-
(2005)
International Solid State Circuits Conference
, vol.1
, pp. 184-185
-
-
Pham, D.1
-
18
-
-
38349009451
-
-
Sony Corporation, Cell architecture
-
Sony Corporation. Sony release: Cell architecture, http://www.scei.co.jp/
-
Sony release
-
-
-
19
-
-
34247349114
-
The potential of the Cell processor for scientific computing
-
ACM Press, New York
-
Williams, S., Shalf, J., Oliker, L., Kamil, S., Husbands, P., Yelick, K.: The potential of the Cell processor for scientific computing. In: Proc. 3rd Conference on Computing Frontiers (CF 2006), pp. 9-20. ACM Press, New York (2006)
-
(2006)
Proc. 3rd Conference on Computing Frontiers (CF
, pp. 9-20
-
-
Williams, S.1
Shalf, J.2
Oliker, L.3
Kamil, S.4
Husbands, P.5
Yelick, K.6
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