HIBI-based multiprocessor soc on FPGA

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3351-3354

  Salminen, Erno ^a   Kulmala, Ari ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION INTERFACE; DESIGN EFFORT; FPGA VENDORS; HARDWARE ACCELERATORS; INTELLECTUAL PROPERTY BLOCKS; IP BLOCK; IP COMPONENTS; LOGIC ELEMENTS; MULTI PROCESSOR SYSTEMS; MULTI-PROCESSOR SOC; NETWORK ON CHIP; OPEN CORE; PROOF OF CONCEPT; SOFT PROCESSOR CORES; SYSTEM ON CHIPS; SYSTEM SPECIFIC; WHOLE SYSTEMS;

CODE CONVERTERS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; INTERNET PROTOCOLS; MULTIPROCESSING SYSTEMS; OPEN CIRCUIT VOLTAGE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33746864021     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465346     Document Type: Conference Paper

References (14)

1. OCP-IP Alliance, Open Core Protocol specification, Release 2.0, 2003.
2. P.G. Paulin, DATE panel: Chips of the future: soft, crunchy or hard?, DATE, Feb. 2004, Vol. 2, pp. 844 - 849.
3. H. Kalte, D. Langen, E. Vonnahme, A. Brinkmann, U. Ruckert, Dynamically reconfigurable system-on-programmable-chip, PDP, Jan. 2002, pp. 235 - 242.
4. I. Mackintosh, Advancing FPGA design efficiency: a proven standard solution, FPGA and Programmable Logic journal, [online], 17th Aug. 2004.
5. E. Salminen et al., HIBI v.2 Communication network for system-onchip, LNCS 3133 Computer Systems: Architectures, Modeling, and Simulation, A.D. Pimentel, S. Vassiliadis, (eds.), Springer-Verlag, Berlin, July 2004, pp. 412 - 422.
6. Altera, Nios 3.0 CPU, Data sheet, Version 2.1, March 2003.
7. M. Collin, M. Nikitovic, R. Haukilahti, SoCrates - a scalable multiprocessor system on chip, MSc thesis, Mälardalen University, May 2000.
8. M. Martina, A. Molino, F. Vacca, FPGA system-on-chip soft IP design: a reconfigurable DSP, MWSCAS, Aug. 2002, Vol. 3, pp. III-196 - III-199.
9. Xiaofang Wang, S.G. Ziavras, Parallel direct solution of linear equations on FPGA-based machines, IPDPS, Apr. 2003, pp. 113 - 120.
10. F. Moraes, N. Calazans, A. Mello, L. Möller, L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, Vol. 38, Iss. 1, Oct. 2004, pp. 69-93.
11. Altera, Avalon Bus Specification Reference Manual, Version 2.3, San Jose, CA, July 2003.
12. T.A. Bartic et al., Highly scalable network on chip for reconfigurable systems, Int'l Symposium on System-on-Chip, Nov. 2003, pp. 79 - 82.
13. C.A. Zeferino, M.E. Kreutz, A.A. Ssin, RASoC: a router soft-core for networks-on-chip, DATE, Feb. 2004, Vol. 3, pp. 198 - 203.
14. T. Kangas, J. Riihimäki, E. Salminen, K. Kuusilinna, T.D. Hämäläinen, Using a Communication Generator in SoC Architecture Exploration Int'l Symposium on System-on-Chip, Nov. 2003, pp. 105- 108.