Power analysis resistant AES implementation with instruction set extensions

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4727 LNCS, Issue , 2007, Pages 303-319

  Tillich, Stefan ^a   Großschädl, Johann ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Advanced encryption standard; Embedded RISC processor; Instruction set extensions; Power analysis; SCA resistance; SPARC V8 architecture

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; COSTS; REDUCED INSTRUCTION SET COMPUTING; SECURITY SYSTEMS; SYSTEMS ANALYSIS;

ADVANCED ENCRYPTION STANDARD; INSTRUCTION SET EXTENSIONS; POWER ANALYSIS;

CRYPTOGRAPHY;

EID: 38049064919     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74735-2_21     Document Type: Conference Paper

References (17)

1. Bertoni, C., Breveglieri, L., Farina, R., Regazzoni, F.: Speeding Up AES By Extending a 32-Bit Processor Instruction Set. In: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), pp. 275-282. IEEE Computer Society, Los Alamitos (2006)
2. Blömer, J., Guajardo, J., Krummel, V.: Provably Secure Masking of AES. In: Handschuh, H., Hasan, M.A. (eds.) SAC 2004. LNCS, vol. 3357, pp. 69-83. Springer, Heidelberg (2004)
3. Bucci, M., Guglielmo, M., Luzzi, R., Trifiletti, A.: A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. In: Mach, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol. 3254, pp. 481-490. Springer, Heidelberg (2004)
4. Elbirt, A.J.: Fast and Efficient Implementation of AES via Instruction Set Extensions. In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007). Workshops Proceedings, Niagara Falls, Canada, May 21-23, 2007, vol. 1, pp. 481-490. IEEE Computer Society Press, Los Alamitos (2007)
5. m). In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 133-147. Springer, Heidelberg (2004)
6. Gürkaynak, F.K., Luethi, P., Bernold, N., Blattmann, R., Goode, V., Marghitola, M., Kaeslin, H., Felber, N., Fichtner, W.: Hardware Evaluation of eSTREAM Candidates: Achterbahn, Grain, MICKEY, MOSQUITO, SFINKS, Trivium, VEST, ZK-Crypt. In: Record of The State of the Art of Stream Ciphers (SASC) Workshop 2006 (February 2006)
7. ISEC project. Instruction Set Extensions for Cryptography (ISEC): Project Webpage, http://www.iaik.tugraz.at/isec
8. Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M.J. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388-397. Springer, Heidelberg (1999)
9. Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks - Revealing the Secrets of Smart Cards. Springer, Heidelberg (2007)
10. Nadehara, K., Ikekawa, M., Kuroda, I.: Extended Instructions for the AES Cryptography and their Efficient Implementation. In: IEEE Workshop on Signal Processing Systems (SIPS'04), Austin, Texas, USA, pp. 152-157. IEEE Press, Los Alamitos (2004)
11. National Institute of Standards and Technology (NIST). FIPS-197: Advanced Encryption Standard (November 2001), Available online at http://www.itl.nist. gov/fipspubs/
12. Schgaguler, K.: Assay of the DPA Vulnerability of Micro Electric Circuits Based on FPGA Measurements. Master's thesis, Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Inffeldgasse 16a, 8010 Graz, Austria (October 2005)
13. Shi, Z., Lee, R.B.: Bit Permutation Instructions for Accelerating Software Cryptography. In: Swartzlander, E.E., Jullien, CA., Schulte, M.J. (eds.) 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), Boston, MA, USA, 10-12 July 2000, pp. 138-148. IEEE Computer Society Press, Los Alamitos (2000)
14. Tillich, S., Großschädl, J.: Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 270-284. Springer, Heidelberg (2006)
15. Tillich, S., Herbst, C., Mangard, S.: Protecting AES Software Implementations on 32-bit Processors against Power Analysis. In: ACNS 2007. LNCS, vol. 4521, pp. 141-157, Springer, Heidelberg (to be published, 2007)
16. Tiri, K., Hwang, D., Hodjat, A., Lai, B.-C., Yang, S., Schaumont, P., Verbauwhede, I.: Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 354-365. Springer, Heidelberg (2005)
17. Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, 16-20 February 2004, vol. 1, pp. 246-251. IEEE Computer Society, Los Alamitos (2004)