Speeding up AES by extending a 32 bit processor instruction set

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 275-279

  Bertoni, Guido Marco ^a   Breveglieri, Luca ^b   Roberto, Farina ^b   Regazzoni, Francesco ^c  

^a STMICROELECTRONICS   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c UNIVERSITY OF LUGANO   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; CRYPTOGRAPHY; EMBEDDED SYSTEMS; OPTIMIZATION; REAL TIME SYSTEMS; SPEED;

AES; CIPHER OPERATIONS; CO-PROCESSORS; INSTRUCTION SET ARCHITECTURE (ISA);

PROGRAM PROCESSORS;

EID: 34547420633     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.62     Document Type: Conference Paper

References (12)

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