Instruction set extensions for efficient AES implementation on 32-bit processors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4249 LNCS, Issue , 2006, Pages 270-284

  Tillich, Stefan ^a   Großschädl, Johann ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Advanced encryption standard; Efficient implementation; Embedded RISC processor; Instruction set extensions; SPARC V8 architecture

Indexed keywords

ALGORITHMS; CELLULAR TELEPHONE SYSTEMS; COMMUNICATION CHANNELS (INFORMATION THEORY); PERSONAL DIGITAL ASSISTANTS; PUBLIC KEY CRYPTOGRAPHY; SENSORS; STORAGE ALLOCATION (COMPUTER);

ADVANCED ENCRYPTION STANDARD (AES); CRYPTOGRAPHIC ALGORITHMS; INSTRUCTION SET EXTENSIONS; SENSOR NODES;

PROGRAM PROCESSORS;

EID: 33750697230     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11894063_22     Document Type: Conference Paper

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