Delay-insensitive gate-level pipelining

Integration, the VLSI Journal

Volumn 30, Issue 2, 2001, Pages 103-131

  Smith, S C ^a   DeMara, R F ^a   Yuan, J S ^a   Hagedorn, M ^b   Ferguson, D ^b  

^a University of Central Florida   (United States)

^b Theseus Logic Inc   (United States)

Author keywords

Asynchronous logic design; Dual rail encoding; NULL convention logic (NCL); Pipelining; Self timed circuits

Indexed keywords

LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; PIPELINE PROCESSING SYSTEMS;

SELF-TIMED CIRCUITS;

VLSI CIRCUITS;

EID: 0035475076     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(01)00013-X     Document Type: Article

References (20)

1. NULL convention logic: A complete and consistent logic for asynchronous digital circuit synthesis
2. Micropipelines
3. Investigation into micropipeline latch design styles
4. High-performance asynchronous pipeline circuits
5. Four-phase micropipeline latch control circuits
6. AMULET3 revealed
7. A low-power, low noise, configurable self-timed DSP
8. Asynchronous wave pipelines for high throughput datapaths
9. Modified asynchronous wave-pipelining
10. Design and performance analysis of delay insensitive multi-ring structures
11. A delay insensitive regular expression recognizer
12. Motorola taps data-driven logic from Theseus for SoC design
13. CMOS circuit design of threshold gates with hysteresis
14. Optimization of NULL convention self-timed circuits
15. System timing
16. An efficient implementation of Boolean functions as self-timed circuits