Regular layout generation of logically optimized datapaths

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1997, Pages 42-47

  Nijssen, R X T ^a   van Eijk, C A J ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ITERATIVE METHODS; LOGIC DESIGN; OPTIMIZATION; VLSI CIRCUITS;

DATAPATH GENERATION; LOGIC CORRESPONDENCE EXTRACTOR; STRUCTURAL NETLIST ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030679964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/267665.267677     Document Type: Conference Paper

References (6)