BoxRouter: A new global router based on box expansion and progressive ILP

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 12, 2007, Pages 2130-2143

  Cho, Minsik ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Congestion; Global routing; Integer linear programming (ILP); Physical design; Rectilinear minimum Steiner tree; Routability

Indexed keywords

ADAPTIVE SYSTEMS; LINEAR PROGRAMMING; MATHEMATICAL MODELS; OPTIMIZATION; TREES (MATHEMATICS);

ADAPTIVE MAZE ROUTING; GLOBAL ROUTING; RECTILINEAR MINIMUM STEINER TREES; ROUTABILITY;

INTEGER PROGRAMMING;

EID: 36348965494     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.907003     Document Type: Article

References (41)

1. http://www.ece.ucsb.edu/~kastner/labyrinth/.
2. R. T. Hadsell and P. H. Madden, "Improved Global Routing through Congestion Estimation," in Proc. Design Automation Conf., June 2003.
3. C. Albrecht, "Global Routing by New Approximation Algorithms for Multicommodity Flow," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, May 2001.
4. M. Pan and C. Chu, "Fastroute 2.0: A high-quality and efficient global router," in Proc. Asia and South Pacific Design Automation Conf., 2007.
5. Z. Cao, T. Jing, J. Xiong, Y. Hu, L. He, and X. Hong, "DpRouter: A Fast and Accurate Dynainic-Pattern-Based Global Routing Algorithm," in Proc. Asia and South Pacific Design Automation Conf., 2007.
6. J. Cong, "Challenges and opportunities for design innovations in nanometer technologies," in SRC Design Science Concept Papers, 1997.
7. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "An Exact Algorithm for Coupling-Free Routing," in Proc. Int. Symp. on Physical Design, April 2001.
8. D. Wu, J. Hu, and R. Mahapatra, "Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment," in Proc. Int. Symp. on Physical Design, April 2005.
9. G. Xu, L. Huang, D. Z. Pan, and D. F. Wong, "Redundant-Via Enhanced Maze Routing for Yield Improvement," in Proc. Asia and South Pacific Design Automation Conf., Jan 2005.
10. L. Huang and D. F. Wong, "Optical Proximity Correction (OPC)-Friendly Maze Routing," in Proc. Design Automation. Conf., June 2004.
11. J. Mitra, P. Yu, and D. Z. Pan, "RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations," in Proc. Design Automation Conf., June 2005.
12. R. Tian, D. F. Wong, and R. Boone, "Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, 2001.
13. T. E. Gbondo-Tugbawa, "Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Process," in PkD. Thesis, Massachusetts Institute of Technology, 2002.
14. K. Sy-Yen, "YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 9, Sep 1993.
15. A. Venkataraman, H. Chen, and I. Koren, "Yield Enhanced Routing for High-Perfonnance VLSI Designs," in Proc. of SPIE the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, Oct 1997.
16. J. Hu and S. Sapatnekar, "A Survey On Multi-net Global Routing for Integrated Circuits," Integration, the VLSI Journal, vol. 31, 2002.
17. _, "A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets," in Proc. Int. Conf. on Computer Aided Design, 2000.
18. J. Lou, S. Krishnamoorthy, and H. S. Sheng, "Estimating Routing Congestion using Probabilistic Analysis," in Proc. Int. Symp. on Physical Design, 2001.
19. A. B. Kahng and X.Xu, "Accurate Pseudo-Constructive Wirelength and Congestion Estimation," in Proc. System-Level Interconnect Prediction, April 2003.
20. J. Westra, C. Bartels, and P. Groeneveld, "Probabilistic Congestion Prediction," in Proc. Int. Symp. on Physical Design, April 2004.
21. C. Sham and E. F. Y. Young, "Congestion Prediction in Early Stages," in Proc. System-Level Interconnect Prediction, April 2005.
22. M. Wang and M. Sarrafzadeh, "Modeling and Minimization of Routing Congestion," in Proc. Design Automation Conf., 2000.
23. J. Westra, C. Bartels, and P. Groeneveld, "Is Probabilistic Congestion Estimation Worthwhile?" in Proc. System-Level Interconnect Prediction, April 2005.
24. M. Burstein and R. Pelavin, "Hierarchical Global Wiring for Custom Chip Design," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 2, no. 4, Oct 1983.
25. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern. Routing: Use and Theory for Increasing Predictability and Avoiding Coupling," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, July 2002.
26. M. Pan and C. Chu, "Fastroute: A step to integrate global routing into placement," in Proc. Int. Conf. on Computer Aided Design, 2006.
27. J. Westra, P. Groeneveld, T. Yan, and P. H. Madden, "Global Routing: Metrics, Benchmarks, and Tools," in IEEE DATC Electronic Design Process, April 2005.
28. X. Yangand, R. Kastner, and M. Sarrafzadeh, "Congestion. Reduction During Placement Based on Integer Programming," in Proc. Int. Conf. on Computer Aided Design.
29. M. Cho, H. Xiang, R. Puri, and D. Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing," in Proc. Int. Conf. on Computer Aided Design, Nov 2006.
30. M. Cho and D. Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP," in Proc. Design Automation Conf., July 2006.
31. H. Ren, D. Z. Pan, C. Alpert, and P. Villarrubia, "Diffusion Based Placement Migration," in Proc. Design Automation Conf., June 2005.
32. X. Yang, B.-K. Choi, and M. Sarrafzadeh, "Routability-driven white space allocation for fixed-die standard-cell placement," April 2003.
33. L. A. Wolsey, "Integer programming," in J. Wiley, 1998.
34. http://www.gnu.org/software/glpk/glpk.html/.
35. G. C. E. Balas, S. Ceria and N. Natraj, "Gomory Cuts Revisited," in Operations Research Letters, vol. 19, no. 1, 1996.
36. A. Osyczka, "Multicriterion optimization in engineering - with fortran programs," in Ellis Horwood, 1984.
37. C. C. N. Chu, "FLUTE: Fast Lookup Table Based Wirelength Estimation Technique," in Proc. Int. Conf. on Computer Aided Design, 2004.
38. D. Warme, "Spanning Trees in Hypergraphs with Applications to Steiner Trees," in Ph.D. Thesis,Computer Science Dept., The University of Virginia, April. 1998.
39. http://www.diku.dk/geosteiner/.
40. H. Ren, D. Z. Pan, C. Alpert, and P. Villarrubia, "Diffusion Based Placement Migration," in Proc. Design Automation Conf., 2005.
41. http://vlsicad.cs.binghamton.edu/.